DRAM power-aware rank scheduling

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2012, Pages 397-402

  Kim, Sukki ^a   Kim, Soontae ^b   Lee, Yebin ^b  

^a LG Electronics Inc   (South Korea)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

dram power and energy efficiency; low power; rank scheduling

Indexed keywords

ACTIVE STATE; CACHE BLOCKS; IDLE TIME; LOW POWER; MEMORY CONTROLLER; PERFORMANCE DEGRADATION; PERFORMANCE LOSS; POWER STATE; POWER-AWARE; SCHEDULING SCHEMES; STATE TRANSITIONS;

CACHE MEMORY; DEGRADATION; ENERGY EFFICIENCY; ENERGY UTILIZATION; LOW POWER ELECTRONICS; SCHEDULING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84865547642     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2333660.2333751     Document Type: Conference Paper

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