Inspection resistant memory: Architectural support for security from physical examination

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 130-141

  Valamehr, Jonathan ^a   Chase, Melissa ^b   Kamara, Seny ^b   Putnam, Andrew ^b   Shumow, Dan ^b   Vaikuntanathan, Vinod ^c   Sherwood, Timothy ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b MICROSOFT RESEARCH   (United States)

^c UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL SUPPORT; HARDWARE SYSTEM; MEMORY TECHNOLOGY; ON CHIP MEMORY; ON CHIPS; PHYSICAL ANALYSIS; SECURITY SCHEME; SIDE EFFECT;

COMPUTER ARCHITECTURE;

HARDWARE;

EID: 84864858804     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237012     Document Type: Conference Paper

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