Assembly process development for fine pitch flip chip silicon-to-silicon 3D wafer level integration with no flow underfill

Journal of Microelectronics and Electronic Packaging

Volumn 7, Issue 3, 2010, Pages 146-151

  Li, Zhaozhi ^a   Lee, Sangil ^b   Lewis, Brian J ^c   Houston, Paul N ^c   Baldwin, Daniel F ^b   Stout, Eugene A ^d   Tessier, Theodore G ^d   Evans, John L ^a  

^a AUBURN UNIVERSITY   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c ENGENT Inc   (United States)

^d FlipChip International LLC   (United States)

Author keywords

Chip floating; Flip chip; No flow underfill; Silicon to on silicon; Underfill voiding; Wafer level packaging

Indexed keywords

CHIP FLOATING; FLIP CHIP; NO-FLOW UNDERFILL; UNDERFILL VOIDING; WAFER LEVEL PACKAGING;

FLIP CHIP DEVICES; SILICON; SILICON WAFERS; THREE DIMENSIONAL;

CHIP SCALE PACKAGES;

EID: 84864646725     PISSN: 15514897     EISSN: None     Source Type: Journal    
DOI: 10.4071/imaps.262     Document Type: Conference Paper

References (11)

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