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Volumn 31, Issue 3, 2008, Pages 519-526

Packaging and assembly of 3-D silicon stacked module for image sensor application

Author keywords

Stacked module; Three dimensional packaging; Three dimensional system in package (SiP); Through silicon via (TSV)

Indexed keywords

ASSEMBLY TECHNOLOGIES; FLIP CHIPS; PROCESS DEVELOPMENT; SENSOR APPLICATIONS; SILICON CARRIERS; STACKED MODULE; THIN FILM METALLIZATION; THREE-DIMENSIONAL PACKAGING; THREE-DIMENSIONAL SYSTEM-IN-PACKAGE (SIP); THROUGH SILICON VIA (TSV); WAFER THINNING; WIRE BONDINGS; WIRE BONDS;

EID: 65349177340     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2008.927826     Document Type: Article
Times cited : (14)

References (11)
  • 1
    • 65349184451 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductor 2006 (ITRS 2006) [Online]. Available: http://www.itrs.net
    • International Technology Roadmap for Semiconductor 2006 (ITRS 2006) [Online]. Available: http://www.itrs.net
  • 3
    • 24644456532 scopus 로고    scopus 로고
    • Design and fabrication of a flip-chip-onchip 3-D packaging structure with a through-silicon via for underfill dispensing
    • Aug
    • Y. K. Tsui and S. W. R. Lee, "Design and fabrication of a flip-chip-onchip 3-D packaging structure with a through-silicon via for underfill dispensing," IEEE Trans. Adv. Packag., vol. 28, no. 3, pp. 413-420, Aug. 2005.
    • (2005) IEEE Trans. Adv. Packag , vol.28 , Issue.3 , pp. 413-420
    • Tsui, Y.K.1    Lee, S.W.R.2
  • 7
    • 65349154496 scopus 로고    scopus 로고
    • Assembly challenges of high density large fine pitch lead-free flip chip package
    • presented at the, San Diego, CA, May-Jun
    • S. C. Chong, Y. M. Tan, T. C. Chai, S. Lim, W. Y. Hnin, and C. K. Cheng, "Assembly challenges of high density large fine pitch lead-free flip chip package," presented at the 56th Electron. Compon. Technol. Conf., San Diego, CA, May-Jun. 2006.
    • (2006) 56th Electron. Compon. Technol. Conf
    • Chong, S.C.1    Tan, Y.M.2    Chai, T.C.3    Lim, S.4    Hnin, W.Y.5    Cheng, C.K.6
  • 8
    • 33845580296 scopus 로고    scopus 로고
    • S. W. Yoon, D.Witarsa, S. Y. L. Lim, V. Ganesh, A. G. K. Viswanath, T. C. Chai, K. O. Navas, and V. Kripesh, Reliability studies of a through via silicon stacked module for 3-D microsystem packaging, presented at the 56th Electron. Compon. Technol. Conf., San Diego, CA, May-Jun. 2006.
    • S. W. Yoon, D.Witarsa, S. Y. L. Lim, V. Ganesh, A. G. K. Viswanath, T. C. Chai, K. O. Navas, and V. Kripesh, "Reliability studies of a through via silicon stacked module for 3-D microsystem packaging," presented at the 56th Electron. Compon. Technol. Conf., San Diego, CA, May-Jun. 2006.
  • 11
    • 84964626561 scopus 로고    scopus 로고
    • Process development for ultra low loop reverse wire bonding on copper bond pad metallization
    • Singapore, Dec
    • V. P. Ganesh, M. Sivakumar, and V. Kripesh, "Process development for ultra low loop reverse wire bonding on copper bond pad metallization," in Proc. 4th Electron. Packag. Technol. Conf., Singapore, Dec. 2002, pp. 356-360.
    • (2002) Proc. 4th Electron. Packag. Technol. Conf , pp. 356-360
    • Ganesh, V.P.1    Sivakumar, M.2    Kripesh, V.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.