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1
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65349184451
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International Technology Roadmap for Semiconductor 2006 (ITRS 2006) [Online]. Available: http://www.itrs.net
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International Technology Roadmap for Semiconductor 2006 (ITRS 2006) [Online]. Available: http://www.itrs.net
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2
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24644519507
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The design of miniature 3-D RF module
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Orlando, FL, May-Jun
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J. Lähteenmäki, J. Miettinen, and P. Heino, "The design of miniature 3-D RF module," in Proc. 55th Electron. Compon. Technol. Conf., Orlando, FL, May-Jun. 2005, pp. 814-817.
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(2005)
Proc. 55th Electron. Compon. Technol. Conf
, pp. 814-817
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Lähteenmäki, J.1
Miettinen, J.2
Heino, P.3
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3
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24644456532
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Design and fabrication of a flip-chip-onchip 3-D packaging structure with a through-silicon via for underfill dispensing
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Aug
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Y. K. Tsui and S. W. R. Lee, "Design and fabrication of a flip-chip-onchip 3-D packaging structure with a through-silicon via for underfill dispensing," IEEE Trans. Adv. Packag., vol. 28, no. 3, pp. 413-420, Aug. 2005.
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(2005)
IEEE Trans. Adv. Packag
, vol.28
, Issue.3
, pp. 413-420
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Tsui, Y.K.1
Lee, S.W.R.2
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4
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24644495782
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Three-dimensional system-in-package using stacked silicon platform technology
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Aug
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V. Kripesh, S. W. Yoon, V. P. Ganesh, O. K. N. Khan, M. D. Rotaru, Q. X. Zhang, W. Fang, and M. K. Iyer, "Three-dimensional system-in-package using stacked silicon platform technology," IEEE Trans. Adv. Packag. vol. 28, no. 3, pp. 377-386, Aug. 2005.
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(2005)
IEEE Trans. Adv. Packag
, vol.28
, Issue.3
, pp. 377-386
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Kripesh, V.1
Yoon, S.W.2
Ganesh, V.P.3
Khan, O.K.N.4
Rotaru, M.D.5
Zhang, Q.X.6
Fang, W.7
Iyer, M.K.8
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5
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33845582687
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Through wafer copper via for silicon based SiP application
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Singapore, Dec
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D.Witarsa, M. Soundarapandian, T. K.Weng, Y. S. Uk, R. Nagarajan, V. Kripesh, and O. K. N. Khan, "Through wafer copper via for silicon based SiP application," in Proc 7th Electron. Packag. Technol. Conf., Singapore, Dec. 2005, pp. 7-12.
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(2005)
Proc 7th Electron. Packag. Technol. Conf
, pp. 7-12
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Witarsa, D.1
Soundarapandian, M.2
Weng, T.K.3
Uk, Y.S.4
Nagarajan, R.5
Kripesh, V.6
Khan, O.K.N.7
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6
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0038350781
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High-density packaging technologies on silicon substrates
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New Orleans, LA, May
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M. Akazawa, S. Kuramochi, T. Maruyama, K. Nakayama, A. Takano, M. Yamaguchi, and Y. Fukuoka, "High-density packaging technologies on silicon substrates," in Proc. 53rd Electron. Compon. Technol. Conf. New Orleans, LA, May 2003, pp. 647-651.
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(2003)
Proc. 53rd Electron. Compon. Technol. Conf
, pp. 647-651
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Akazawa, M.1
Kuramochi, S.2
Maruyama, T.3
Nakayama, K.4
Takano, A.5
Yamaguchi, M.6
Fukuoka, Y.7
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7
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65349154496
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Assembly challenges of high density large fine pitch lead-free flip chip package
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presented at the, San Diego, CA, May-Jun
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S. C. Chong, Y. M. Tan, T. C. Chai, S. Lim, W. Y. Hnin, and C. K. Cheng, "Assembly challenges of high density large fine pitch lead-free flip chip package," presented at the 56th Electron. Compon. Technol. Conf., San Diego, CA, May-Jun. 2006.
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(2006)
56th Electron. Compon. Technol. Conf
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Chong, S.C.1
Tan, Y.M.2
Chai, T.C.3
Lim, S.4
Hnin, W.Y.5
Cheng, C.K.6
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8
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33845580296
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S. W. Yoon, D.Witarsa, S. Y. L. Lim, V. Ganesh, A. G. K. Viswanath, T. C. Chai, K. O. Navas, and V. Kripesh, Reliability studies of a through via silicon stacked module for 3-D microsystem packaging, presented at the 56th Electron. Compon. Technol. Conf., San Diego, CA, May-Jun. 2006.
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S. W. Yoon, D.Witarsa, S. Y. L. Lim, V. Ganesh, A. G. K. Viswanath, T. C. Chai, K. O. Navas, and V. Kripesh, "Reliability studies of a through via silicon stacked module for 3-D microsystem packaging," presented at the 56th Electron. Compon. Technol. Conf., San Diego, CA, May-Jun. 2006.
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9
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33845582057
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Development of 3-D stack package using silicon interposer for high power application
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presented at the, San Diego, CA, May-Jun
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N. Khan, S. W. Yoon, V. P. Ganesh, A. G. K. Viswanath, Ranganathan, D. Witarsa, S. Lim, V. Kripesh, and D. Pinjala, "Development of 3-D stack package using silicon interposer for high power application," presented at the 56th Electron. Compon. Technol. Conf., San Diego, CA, May-Jun. 2006.
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(2006)
56th Electron. Compon. Technol. Conf
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Khan, N.1
Yoon, S.W.2
Ganesh, V.P.3
Viswanath, A.G.K.4
Ranganathan5
Witarsa, D.6
Lim, S.7
Kripesh, V.8
Pinjala, D.9
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10
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24644451625
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Key challenges in fine pitch bumped wafer mechanical back grinding and polishing
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Tokyo, Japan, Apr
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V. P. Ganesh, S. Lim, D. Witarsa, M. Kumar, L. A. Lim, S. W. Yoon, and V. Kripesh, "Key challenges in fine pitch bumped wafer mechanical back grinding and polishing," in Proc. Int. Conf. Electron. Packag., Tokyo, Japan, Apr. 2003, pp. 260-265.
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(2003)
Proc. Int. Conf. Electron. Packag
, pp. 260-265
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Ganesh, V.P.1
Lim, S.2
Witarsa, D.3
Kumar, M.4
Lim, L.A.5
Yoon, S.W.6
Kripesh, V.7
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11
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84964626561
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Process development for ultra low loop reverse wire bonding on copper bond pad metallization
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Singapore, Dec
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V. P. Ganesh, M. Sivakumar, and V. Kripesh, "Process development for ultra low loop reverse wire bonding on copper bond pad metallization," in Proc. 4th Electron. Packag. Technol. Conf., Singapore, Dec. 2002, pp. 356-360.
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(2002)
Proc. 4th Electron. Packag. Technol. Conf
, pp. 356-360
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Ganesh, V.P.1
Sivakumar, M.2
Kripesh, V.3
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