Yield analysis and process modeling of low cost, high throughput flip chip assembly based on no-flow underfill materials

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 24, Issue 2, 2001, Pages 123-135

  Thorpe, Ryan ^b   Baldwin, Daniel F ^a,b   Smith, Brian ^b   McGovern, Lawrence ^b  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Area array packaging; Electronics manufacturing; Electronics packaging; Flip chip; No flow underfills; Reflowable encapsulants; Solder interconnects; Underfills; Yield analysis

Indexed keywords

AREA ARRAY PACKAGING; NO FLOW UNDERFILLS; REFLOWABLE ENCAPSULANTS; SOLDER INTERCONNECTS; YIELD ANALYSIS;

CURING; EPOXY RESINS; FLIP CHIP DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE; SUBSTRATES; SURFACE MOUNT TECHNOLOGY; THERMAL EFFECTS;

ELECTRONICS PACKAGING;

EID: 0035301154     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/6104.930963     Document Type: Article

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