Executing synchronous dataflow graphs on a SPM-based multicore architecture

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 664-671

  Choi, Junchul ^a   Oh, Hyunok ^b   Kim, Sungchan ^b   Ha, Soonhoi ^c  

^a Seoul National University   (South Korea)

^b Hanyang University   (South Korea)

^c Chonbuk National University   (South Korea)

Author keywords

memory overlay; multicore architecture; multiprocessor scheduling; prefetching; scratch pad memory; synchronous dataflow

Indexed keywords

MULTI PROCESSOR SCHEDULING; MULTICORE ARCHITECTURES; PREFETCHING; SCRATCH PAD MEMORY; SYNCHRONOUS DATAFLOW;

COMPUTER AIDED DESIGN; RESPONSE TIME (COMPUTER SYSTEMS); SCHEDULING; SOFTWARE ARCHITECTURE;

MULTIPROCESSING SYSTEMS;

EID: 84863545495     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228480     Document Type: Conference Paper

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