Hybrid code-data prefetch-aware multiprocessor task graph scheduling

Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011

Volumn , Issue , 2011, Pages 583-590

  Damavandpeyma, Morteza ^a   Stuijk, Sander ^a   Basten, Twan ^a,b   Geilen, Marc ^a   Corporaal, Henk ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b EMBEDDED SYSTEMS INSTITUTE   (Netherlands)

Author keywords

Code generation; ILP; Run time minimization; Scheduling; Scratchpad memory

Indexed keywords

CODE GENERATION; DATA-DRIVEN; ILP; INTEGER LINEAR PROGRAMMING; MP3 DECODERS; MULTIPROCESSOR SYSTEM ON CHIPS; MULTIPROCESSOR TASKS; ON CHIP MEMORY; PARALLEL TASK; PERFORMANCE BOTTLENECKS; PREFETCHING; RUNTIMES; SCHEDULING TECHNIQUES; SCRATCH PAD MEMORY; TASK GRAPH; TASK-SCHEDULING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; IMAGE CODING; INTEGER PROGRAMMING; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PROGRAM PROCESSORS; SYSTEMS ANALYSIS;

SCHEDULING;

EID: 80055019115     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2011.80     Document Type: Conference Paper

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