Scheduling of synchronous data flow models on scratchpad memory based embedded processors

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2010, Pages 205-212

  Che, Weijia ^a   Chatha, Karam S ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CODES (SYMBOLS); COMPUTER AIDED DESIGN; DATA FLOW ANALYSIS; INTEGER PROGRAMMING; MEMORY ARCHITECTURE; OPTIMAL SYSTEMS; SCHEDULING;

BENCHMARK APPLICATIONS; EMBEDDED PROCESSORS; EMBEDDED SYSTEM APPLICATIONS; INTEGER LINEAR PROGRAMMING; LOWER-POWER CONSUMPTION; NETWORK PROCESSING; SCRATCH PAD MEMORY; SYNCHRONOUS DATAFLOW;

RESPONSE TIME (COMPUTER SYSTEMS);

EID: 78650916761     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2010.5654150     Document Type: Conference Paper

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