Ultra low power computing with sub-threshold leakage: A comparative study of bulk and SOI technologies

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Raychowdhury, A ^a   Paul, B C ^a   Bhunla, S ^b   Roy, K ^a  

^a PURDUE UNIVERSITY   (United States)

^b CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; HIERARCHICAL SYSTEMS; LEAKAGE CURRENTS; SYSTEMS ANALYSIS;

SUB-THRESHOLD LEAKAGE; ULTRA LOW POWER COMPUTING;

SILICON ON INSULATOR TECHNOLOGY;

EID: 34047174862     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243768     Document Type: Conference Paper

References (7)

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3. B. Paul et al., "Device optimization for ultraslow power digital subthreshold operation", ISLPED, pp. 96-101, 2004.
4. Well Tempered MOSFET: http://www-mtl.mit.edu/Well
5. H. Soeleman, "Robust Sub-threshold Logic for Ultralow Power Operation", TVLSI, Vol. 9, No. 1, pp. 90-99, 2001.
6. J. Rabaey, "Digital Integrated Circuits", Prentice Hall
7. J. Kim et al. "Double Gate MOSFET Sub-threshold Circuit for Ultralow Power Applications", TED, VOl 51, 9, Sept 2004.