An innovative ultra low voltage sub-32nm sram voltage sense amplifier in DG-SOI technology

Midwest Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 205-208

  Pranav, Pranav ^a,b   Giraud, Bastien ^b   Amara, Amara ^b  

^a VIT UNIVERSITY   (India)

^b Institut Superieur d'Electronique de Paris ISEP   (France)

Author keywords

[No Author keywords available]

Indexed keywords

GALERKIN METHODS; MOSFET DEVICES; RELIABILITY; RELIABILITY ANALYSIS; SILICON; ULSI CIRCUITS;

FULLY DEPLETED; HIGH-PERFORMANCE; LOW-VOLTAGE; MONTE CARLO ANALYSES; PROCESS VARIATIONS; PROPOSED ARCHITECTURES; SELF-ALIGNED; SENSING; SILICON-ON-INSULATOR; SOI CIRCUITS; SOI TECHNOLOGIES; VOLTAGE SENSES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 54249088127     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2008.4616772     Document Type: Conference Paper

References (6)

1. Rongtian Zhang, Kaushik Roy, and David B. Janes, "Double-Gate Fully-Depleted SOI Transistors for Low-Power High-Performance Nano-Scale Circuit Design", ISLPED'01, August 6-7, 2001, Huntington Beach, California, USA
2. Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, and Kaushik Roy, "Statistical characterization and on-chip measurement methods for local random variability of a process using sense-amplifier-based test structure", ISSCC, february 2007 San Francisco, CA, USA
3. Saibal Mukhopadhyay, Hamid Mahmoodi, and Kaushik Roy, "Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET", March 2005, San Jose, CA, USA.
4. Hong-Yi Huang, and Shih-Lun Chen, "Self-isolated gain-enhanced sense amplifier", ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference, pp. 57-60
5. Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara, "An Innovative sub-32nm SRAM Voltage Sense Amplifier in Double-Gate CMOS Insensitive to Process Variations and Transistor Mismatch", unpublished.
6. Bastien Giraud and Amara Amara, "Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS", DELTA, January 2008, Hong Kong.