A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder

2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010

Volumn , Issue , 2010, Pages 78-81

  Clerc, Sylvain ^a   Abouzeid, Fady ^c   Heinrich, Vincent ^a   Jain, Abhishek ^a   Veggetti, Andrea Mario ^a   Crippa, Dennis ^a   Roche, Philippe ^a   Sicard, Gilles ^b  

^a STMICROELECTRONICS   (Italy)

^b TIMA LABORATORY   (France)

^c NONE

Author keywords

40nm CMOS digital circuit design; Low power; Ultra low voltage

Indexed keywords

CMOS DIGITAL CIRCUITS; ENERGY-CONSTRAINED; FORWARD BIAS; INDUSTRIAL IMPLEMENTATION; LOW POWER; OPERATING VOLTAGE; PROCESS EFFECTS; STANDARD CELL; ULTRA-LOW-VOLTAGE;

DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC BATTERIES; INDUSTRIAL APPLICATIONS; INTEGRATED CIRCUITS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 77955637295     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2010.5510284     Document Type: Conference Paper

References (9)

1. K Roy, S Mukhopadhyay, H Mahmoodi, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep- Submicrometer CMOS Circuits", International Symposium on Low Power Electronic Design, 2004
2. A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," Solid-State Circuits, IEEE Journal of , vol.40, no.1, pp. 310-319, Jan. 2005
3. J. Wang, J.-S. Chen, Y.-M. Wang and C. Yeh, "A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS," Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International , vol., no., pp.294-604, 11-15 Feb. 2007
4. M.-E. Hwang, A. Raychowdhury, K. Kim and K. Roy, "A 85mV 40nW Process-Tolerant Subthreshold 8x8 FIR Filter in 130nm Technology," VLSI Circuits, 2007 IEEE Symposium on , vol., no., pp.154-155, 14-16 June 2007
5. F Abouzeid, S Clerc, M Renaudin, G Sicard, "Ultra-Low Voltage from 65nm to 32nm", Faible Tension Faible Consommation 2009.
6. F. Abouzeid, S. Clerc, F. Firmin, M. Renaudin and G. Sicard, "A 45nm CMOS 0.35V-Optimized Standard Cell Library for Ultra-Low Power Applications", International Symposium on Low Power Electronic Design, August 2009
7. S Clerc, F Abouzeid, V Heinrich, A Kumar, "towards an Ultra Low Voltage 40 nm CMOS design platform", International Symposium on Low Power Electronic Design, August 2010 (under review).
8. R.C. Bose and D.K. Ray-Chaudhuri, "On a class of error correcting binary group Codes", Information and Control, 3, pp. 68-79, March 1960
9. P. Urard, E. Yeo, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Lantreibecq, and B. Gupta, "A 135Mb/s DVB-S2 Compliant Codec Based on 64,800b LDPC and BCH Codes", Proc. IEEE ISSCC 2005, pp. 446-447, Feb 6-10, 2005