A low leakage SRAM macro with replica cell biasing scheme

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 4, 2006, Pages 815-822

  Takeyama, Yasuhisa ^a   Otake, Hiroyuki ^a   Hirabayashi, Osamu ^a   Kushida, Keiichi ^a   Otsuka, Nobuaki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Replica cell; Sleep mode; SRAM; Standby leakage

Indexed keywords

CLAMPING DEVICES; COMPUTER PERIPHERAL EQUIPMENT; LEAKAGE CURRENTS; OPTIMIZATION; VOLTAGE CONTROL;

REPLICA CELL; SLEEP MODE; STANDBY LEAKAGE;

STATIC RANDOM ACCESS STORAGE;

EID: 33645679741     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870763     Document Type: Conference Paper

References (7)

1. S. Mutoh et al., "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
2. T. Douseki et al., "A 0.5 V SIMOX-MTCMOS circuit with 200 ps logic gate," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1996, pp. 84-85.
3. S. Mutoh et al., "A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1996, pp. 168-169.
4. K. Osada et al., "16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1952-1957, Nov. 2003.
5. K. Nii et al., "A 90-nm low-power 32 KByte embedded SRAM with gate leakage suppression circuit for mobile applications," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 684-693, Apr. 2004.
6. M. Yamaoka et al., "A 300 MHz 25 μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 186-194, Jan. 2005.
7. C. H. Kim et al., "A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations," IEEE Trans. Very Large Scale Integmt. (VLSI) Syst., vol. 13, no. 3, pp. 349-357, Mar. 2005.