Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2011, Pages 563-570

  Jung, Moongon ^a   Liu, Xi ^a   Sitaraman, Suresh K ^a   Pan, David Z ^b   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; DESIGN OPTIMIZATION; DIELECTRIC LINERS; INTERFACIAL CRACKS; MECHANICAL RELIABILITY; RESPONSE SURFACE METHOD; THERMO-MECHANICAL STRESS; THROUGH-SILICON-VIA;

COMPUTER AIDED ANALYSIS; COMPUTER AIDED DESIGN; DESIGN OF EXPERIMENTS; OPTIMIZATION; STRESSES; THREE DIMENSIONAL;

CRACKS;

EID: 84862928895     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2011.6105386     Document Type: Conference Paper

References (9)

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