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Volumn , Issue , 2008, Pages 87-90

Composability in the time-triggered System-on-Chip architecture

Author keywords

[No Author keywords available]

Indexed keywords

COMPOSABILITY; IP-CORES; PROTOTYPE IMPLEMENTATIONS; SEAMLESS INTEGRATION; TIME-TRIGGERED SYSTEMS;

EID: 67650220948     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2008.4641485     Document Type: Conference Paper
Times cited : (14)

References (10)
  • 2
    • 27344456043 scopus 로고    scopus 로고
    • The Æthereal network on chip: Concepts, architectures, and implementations
    • K. Goossens, J. Dielissen, and A. Radulescu. "The Æthereal network on chip: Concepts, architectures, and implementations", IEEE Design and Test of Computers, vol. 22, no.5, 2005.
    • (2005) IEEE Design and Test of Computers , vol.22 , Issue.5
    • Goossens, K.1    Dielissen, J.2    Radulescu, A.3
  • 7
    • 34547376702 scopus 로고
    • Version 2.0. Robert Bosch Gmbh, Stuttgart, Germany
    • Bosch. CAN Specification, Version 2.0. Robert Bosch Gmbh, Stuttgart, Germany. 1991.
    • (1991) Specification
    • Bosch, C.A.N.1
  • 9
    • 53549126756 scopus 로고    scopus 로고
    • Interface Design in the Time-Triggered System-on-Chip Architecture
    • Ph.D. thesis, Vienna University of Technology, Institute of Computer Engineering, January
    • C. El Salloum, "Interface Design in the Time-Triggered System-on-Chip Architecture", Ph.D. thesis, Vienna University of Technology, Institute of Computer Engineering, January 2008.
    • (2008)
    • El Salloum, C.1
  • 10
    • 0010243431 scopus 로고
    • Replica Determinism in Fault-Tolerant Real-Time Systems
    • Ph.D. thesis, Vienna University of Technology, Institute of Computer Engineering, April
    • S. Poledna, "Replica Determinism in Fault-Tolerant Real-Time Systems", Ph.D. thesis, Vienna University of Technology, Institute of Computer Engineering, April 1994.
    • (1994)
    • Poledna, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.