Self-adaptive NoC power management with dual-level agents: Architecture and implementation

PECCS 2012 - Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems

Volumn , Issue , 2012, Pages 450-458

  Jafri, Syed M A H ^a,b,c   Guang, Liang ^b,c   Jantsch, Axel ^a   Paul, Kolin ^d   Hemani, Ahmed ^a   Tenhunen, Hannu ^a,b,c  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^b UNIVERSITY OF TURKU   (Finland)

^c TURKU CENTRE FOR COMPUTER SCIENCE   (Finland)

^d INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

Agent based design; DVFS; Hardware software co design; Low power design; Multiprocessor architectures

Indexed keywords

AGENT-BASED DESIGN; DVFS; HARDWARE/SOFTWARE CO-DESIGN; LOW-POWER DESIGN; MULTI PROCESSOR ARCHITECTURE;

ARCHITECTURAL DESIGN; COMMUNICATION SYSTEMS; COMPUTER AIDED DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; ENERGY MANAGEMENT; HARDWARE; OPTIMIZATION; PROGRAM PROCESSORS;

SOFTWARE AGENTS;

EID: 84862118402     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. Asanovic, K., Bodik, R., Catanzaro, B. C., Gebis, J. J., Husbands, P., Keutzer, K., Patterson, D. A., Plishker, W. L., Shalf, J., Williams, S. W., and Yelick, K. A. (2006). The landscape of parallel computing research: A view from berkeley. Technical report, U.C.Berkeley.
2. Borkar, S., Karnik, T., Narendra, S., Tschanz, J., Keshavarzi, A., and De, V. (2003). Parameter variations and impact on circuits and microarchitecture. In Proc. Design Automation Conference, pages 338-342.
3. Chabloz, J. M. and Hemani, A. (2010). Distributed dvfs using rationally-related frequencies and discrete voltage levels. In Low-Power Electronics and Design (ISLPED), 2010 ACM/IEEE International Symposium on, pages 247 -252.
4. Chen, X., Lu, Z., Jantsch, A., and Chen, S. (2010). Supporting distributed shared memory on multi-core networkon- chips using a dual microcoded controller. In Proc. Design, Automation & Test in Europe Conf. & Exhibition (DATE), pages 39-44.
5. Ciordas, C. (2008). Monitoring-Aware Network-on-Chip Design. PhD thesis, Eindhoven University of Technology.
6. Ciordas, C., Hansson, A., Goossens, K., and Basten, T. (2008). A monitoring-aware network-on-chip design flow. J. Syst. Archit., 54:397-410.
7. Dafali, R. and Diguet, J.-P. (2009). Self-adaptive network interface (sani): Local component of a noc configuration manager. In Proc. Int. Conf. Reconfigurable Computing and FPGAs ReConFig'09, pages 296-301.
8. Guang, L., Nigussie, E., Isoaho, J., Rantala, P., and Tenhunen, H. (2010). Interconnection alternatives for hierarchical monitoring communication in parallel socs. Microprocessors and Microsystems, 34(5):118-128.
9. Hoffmann, H., Eastep, J., Santambrogio, M. D., Miller, J. E., and Agarwal, A. (2010). Application heartbeats for software performance and health. In Proceedings of the 15th ACM SIGPLAN symposium on Principles and practice of parallel programming, PPoPP'10, pages 347-348, New York, NY, USA. ACM.
10. Howard, J., Dighe, S., Vangal, S. R., Ruhl, G., Borkar, N., Jain, S., Erraguntla, V., Konow, M., Riepen, M., Gries, M., Droege, G., Lund-Larsen, T., Steibl, S., Borkar, S., De, V. K., and Van Der Wijngaart, R. (2011). A 48-core ia-32 processor in 45 nm cmos using on-die message-passing and dvfs for performance and power scaling. IEEE Journal of Solid-State Circuits, 46(1):173-183.
11. Jean-Michel Chabloz, A. H. (2012). Scalable Multicore Architectures, chapter PowerManagement ArchitectureinMcNoC, pages 55-80. Springer Science+ Business Media, LLC.
12. Nostrum (2011). http://www.ict.kth.se/nostrum/.
13. Rabaey, J. M. (2007). Scaling the power wall: Revisiting the low-power design rules. Keynote speech at SoC 07 Symposium.
14. Salehie, M. and Tahvildari, L. (2009). Self-adaptive software: Landscape and research challenges. ACM Trans. Auton. Adapt. Syst., 4:14:1-14:42.
15. Sylvester, D., Blaauw, D., and Karl, E. (2006). Elastic: An adaptive self-healing architecture for unpredictable silicon. IEEE Design & Test of Computers, 23(6):484-490.
16. Truong, D., Cheng, W., Mohsenin, T., Yu, Z., Jacobson, A., Landge, G., Meeuwsen, M., Watnik, C., Tran, A., Xiao, Z., Work, E., Webb, J., Mejia, P., and Baas, B. (2009). A 167-processor computational platform in 65 nm cmos. IEEE Journal of Solid State Circuits, 44(4):1130-1144.
17. van Berkel, C. (2009). Multi-core for mobile phones. In Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE'09.