Distributed DVFS using rationally-related frequencies and discrete voltage levels

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2010, Pages 247-252

  Chabloz, J M ^a   Hemani, A ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

Design

Indexed keywords

CLOCK FREQUENCY; DISCRETE VOLTAGE; ENERGY BENEFITS; LATENCY-INSENSITIVE DESIGNS; PERFORMANCE BENEFITS; VOLTAGE LEVELS;

POWER ELECTRONICS;

DESIGN;

EID: 77957948826     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1840845.1840897     Document Type: Conference Paper

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