Interconnection alternatives for hierarchical monitoring communication in parallel SoCs

Microprocessors and Microsystems

Volumn 34, Issue 5, 2010, Pages 118-128

  Guang, Liang ^a   Nigussie, Ethiopia ^a   Isoaho, Jouni ^a   Rantala, Pekka ^a   Tenhunen, Hannu ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

Hierarchical monitoring services; Interconnection architectures; Network on Chip; Quality of service

Indexed keywords

65NM TECHNOLOGY; AGENT MONITORING; BASE-LINE ARCHITECTURE; BEST-EFFORT SERVICES; DATA TRAFFIC; DESIGN PARADIGM; DISTRIBUTED AGENTS; FLEXIBLE RECONFIGURATION; INTERCONNECTION ARCHITECTURE; MICROBENCHMARKS; MONITORING NETWORK; MONITORING SERVICES; NETWORK ON CHIP; ON-CHIP INTERCONNECTION; PARALLEL EMBEDDED SYSTEMS; PARALLEL SYSTEM; POWER ESTIMATIONS; SCALABLE APPROACH; TRAFFIC CLASS; TRAFFIC TRACES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION; DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; HIERARCHICAL SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; QUALITY CONTROL; QUALITY OF SERVICE; TELECOMMUNICATION SERVICES; TIME DIVISION MULTIPLE ACCESS; VLSI CIRCUITS;

MONITORING;

EID: 77955198710     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2009.12.002     Document Type: Conference Paper

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