-
1
-
-
84943817322
-
Error detecting and error correcting codes
-
Apr.
-
R. W. Hamming, "Error detecting and error correcting codes," Bell Syst. Tech. J., vol. 29, no. 2, pp. 147-160, Apr. 1950.
-
(1950)
Bell Syst. Tech. J.
, vol.29
, Issue.2
, pp. 147-160
-
-
Hamming, R.W.1
-
2
-
-
29344472607
-
Radiation-induced soft errors in advanced semiconductor technologies
-
Sep.
-
R. C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 301-316, Sep. 2005.
-
(2005)
IEEE Trans. Device Mater. Rel.
, vol.5
, Issue.3
, pp. 301-316
-
-
Baumann, R.C.1
-
3
-
-
0021392066
-
Error-correcting codes for semiconductor memory applications: A state-of-the-art review
-
C. L. Chen and M. Y. Hsiao, "Error-correcting codes for semiconductor memory applications: A state-of-The-art review," IBM J. Res. Develop., vol. 28, no. 2, pp. 124-134, Mar. 1984. (Pubitemid 14546564)
-
(1984)
IBM Journal of Research and Development
, vol.28
, Issue.2
, pp. 124-134
-
-
Chen, C.L.1
Hsiao, M.Y.2
-
4
-
-
0027239138
-
Optimized state assignment of Single fault tolerant FSMs based on SEC codes
-
R. Leveugle, "Optimized state assignment of single fault tolerant FSMs based on SEC codes," in Proc. 30th Conf. Des. Autom., Jun. 1993, pp. 14-18. (Pubitemid 23673295)
-
(1993)
Proceedings - Design Automation Conference
, pp. 14-18
-
-
Leveugle, R.1
-
5
-
-
77949390552
-
Multi-bit error correction methods for latency-constrained flash memory systems
-
Mar.
-
P. Ankolekar, S. Rosner, R. Isaac, and J. Bredow, "Multi-bit error correction methods for latency-constrained flash memory systems," IEEE Trans. Device Mater. Rel., vol. 10, no. 1, pp. 33-39, Mar. 2010.
-
(2010)
IEEE Trans. Device Mater. Rel.
, vol.10
, Issue.1
, pp. 33-39
-
-
Ankolekar, P.1
Rosner, S.2
Isaac, R.3
Bredow, J.4
-
6
-
-
62949103821
-
Fault secure encoder and decoder for nanoMemory applications
-
Apr.
-
H. Naeimi and A. DeHon, "Fault secure encoder and decoder for nanoMemory applications," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 4, pp. 473-486, Apr. 2009.
-
(2009)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.17
, Issue.4
, pp. 473-486
-
-
Naeimi, H.1
DeHon, A.2
-
7
-
-
0014823837
-
A class of optimal minimum odd-weight column SEC-DED codes
-
Jul.
-
M. Y. Hsiao, "A class of optimal minimum odd-weight column SEC-DED codes," IBM J. Res. Develop., vol. 14, no. 4, pp. 395-401, Jul. 1970.
-
(1970)
IBM J. Res. Develop.
, vol.14
, Issue.4
, pp. 395-401
-
-
Hsiao, M.Y.1
-
8
-
-
52049098657
-
New linear SEC-DED codes with reduced triple bit error miscorrection probability
-
Jul.
-
M. Richter, K. Oberlaender, and M. Goessel, "New linear SEC-DED codes with reduced triple bit error miscorrection probability," in Proc. 14th IEEE IOLTS, Jul. 2008, pp. 37-42.
-
(2008)
Proc. 14th IEEE IOLTS
, pp. 37-42
-
-
Richter, M.1
Oberlaender, K.2
Goessel, M.3
-
9
-
-
77954030094
-
Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule
-
Jul.
-
E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, "Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule," IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1527-1538, Jul. 2010.
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, Issue.7
, pp. 1527-1538
-
-
Ibe, E.1
Taniguchi, H.2
Yahagi, Y.3
Shimbo, K.4
Toba, T.5
-
10
-
-
58849088491
-
Single event effect induced multiple-cell upsets in a commercial 90 nm CMOS digital technology
-
Dec.
-
R. K. Lawrence and A. T. Kelly, "Single event effect induced multiple-cell upsets in a commercial 90 nm CMOS digital technology," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 3367-3374, Dec. 2008.
-
(2008)
IEEE Trans. Nucl. Sci.
, vol.55
, Issue.6
, pp. 3367-3374
-
-
Lawrence, R.K.1
Kelly, A.T.2
-
11
-
-
0033737766
-
Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's
-
Jun.
-
S. Satoh, Y. Tosaka, and S. A. Wender, "Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's," IEEE Electron Device Lett., vol. 21, no. 6, pp. 310-312, Jun. 2000.
-
(2000)
IEEE Electron Device Lett.
, vol.21
, Issue.6
, pp. 310-312
-
-
Satoh, S.1
Tosaka, Y.2
Wender, S.A.3
-
12
-
-
69549118775
-
SRAM interleaving distance selection with a soft error failure model
-
Aug.
-
S. Baeg, S. Wen, and R. Wong, "SRAM interleaving distance selection with a soft error failure model," IEEE Trans. Nucl. Sci., vol. 56, no. 4, pp. 2111-2118, Aug. 2009, Part 2.
-
(2009)
IEEE Trans. Nucl. Sci.
, vol.56
, Issue.4 PART 2
, pp. 2111-2118
-
-
Baeg, S.1
Wen, S.2
Wong, R.3
-
13
-
-
40649121796
-
A novel approach to improving burst errors correction capability of Hamming code
-
Jul.
-
J. Zhao and Y. Shi, "A novel approach to improving burst errors correction capability of Hamming code," in Proc. Int. Conf. Commun., Circuits Syst., Jul. 2007, pp. 1193-1196.
-
(2007)
Proc. Int. Conf. Commun., Circuits Syst.
, pp. 1193-1196
-
-
Zhao, J.1
Shi, Y.2
-
14
-
-
37549069366
-
Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC code
-
May
-
A. Dutta and N. A. Touba, "Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC code," in Proc. 25th IEEE VLSI Test Symp., May 2007, pp. 349-354.
-
(2007)
Proc. 25th IEEE VLSI Test Symp.
, pp. 349-354
-
-
Dutta, A.1
Touba, N.A.2
-
15
-
-
77951025056
-
Minimizing soft errors in TCAM devices: A probabilistic approach to determining scrubbing intervals
-
Apr.
-
S. Baeg, S.Wen, and R.Wong, "Minimizing soft errors in TCAM devices: A probabilistic approach to determining scrubbing intervals," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 4, pp. 814-822, Apr. 2010.
-
(2010)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.57
, Issue.4
, pp. 814-822
-
-
Baeg, S.1
Wen, S.2
Wong, R.3
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