Bit-level abstraction in the verification of pipelined microprocessors by correspondence checking

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1522, Issue , 1998, Pages 18-35

  Velev, Miroslav N ^a   Bryant, Randal E ^b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b Carnegie Mellon University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; COMPUTER AIDED DESIGN; ENCODING (SYMBOLS); FORMAL METHODS; SIGNAL ENCODING;

ABSTRACTION METHODS; CORRESPONDENCE CHECKING; EFFICIENT ENCODING; EFFICIENT MEMORY MODELING; ENCODING TECHNIQUES; SYMBOLIC SIMULATION; SYMMETRY REDUCTION; UNINTERPRETED FUNCTIONS;

PIPELINES;

EID: 84948966443     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-49519-3_3     Document Type: Conference Paper

References (21)

1. S. Berezin, A. Biere, E.M. Clarke, and Y. Zhu, “Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification,” FMCAD’98 (appears in this publication).
2. S. Bose, and A.L. Fisher, “Verifying Pipelined Hardware Using Symbolic Logic Simulation,” International Conference on Computer Design, October 1989, pp. 217-221.
3. R.E. Bryant, “Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams,” ACM Computing Serveys, Vol. 24, No. 3 (September 1992), pp. 293-318.
4. R.E. Bryant, and M.N. Velev, “Verification of Pipelined Microprocessors by Comparing Memory Execution Sequences in Symbolic Simulation,”2 Asian Computer Science Conference (ASIAN’97), R.K. Shyamasundar and K. Ueda, eds., LNCS 1345, Springer-Verlag, December 1997, pp. 18-31.
5. J.R. Burch, and D.L. Dill, “Automated Verification of Pipelined Microprocessor Control,” CAV‘94, D.L. Dill, ed., LNCS 818, Springer-Verlag, June 1994, pp. 68-80.
6. J.R. Burch, “Techniques for Verifying Superscalar Microprocessors,” DAC‘96, June 1996, pp. 552-557.
7. Y.-A. Chen, “Arithmetic Circuit Verification Based on Word-Level Decision Diagrams,” Ph.D. thesis, School of Computer Science, Carnegie Mellon University, May 1998.
8. A. Goel, K. Sajid, H. Zhou, A. Aziz, and V. Singhal, “BDD Based Procedures for a Theory of Equality with Uninterpreted Functions,” CAV‘98, June, 1998.
9. C.A.R. Hoare, “Proof of Correctness of Data Representations,” Acta Informatica, 1972, Vol.1, pp. 271-281.
10. R. Hojati, A. Kuehlmann, S. German, and R.K. Brayton, “Validity Checking in the Theory of Equality with Uninterpreted Functions Using Finite Instantiations,” International Workshop on Logic Synthesis, May 1997.
11. A. Jain, “Formal Hardware Verification by Symbolic Trajectory Evaluation,” Ph.D. thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, August 1997.
12. T.-H. Liu, K. Sajid, A. Aziz, and V. Singhal, “Optimizing Designs Containing Black Boxes,” 34th Design Automation Conference, June 1997, pp. 113-116.
13. G. Nelson, and D.C. Oppen, “Simplification by Cooperating Decision Procedures,” ACM Transactions on Programming Languages and Systems, Vol. 1, No. 2, October 1979, pp. 245-257.
14. M. Pandey, “Formal Verification of Memory Arrays,” Ph.D. thesis, School of Computer Science, Carnegie Mellon University, May 1997.
15. D.A. Patterson, and J.L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 2nd Edition, Morgan Kaufmann Publishers, San Francisco, CA, 1998.
16. C.-J.H. Seger, and R.E. Bryant, “Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories,” Formal Methods in System Design, Vol. 6, No. 2, March 1995, pp. 147-190.
17. R.E. Shostak, “A Practical Decision Procedure for Arithmetic with Function Symbols,” J. ACM, Vol. 26, No. 2, April 1979, pp. 351-360.
18. M.N. Velev, R.E. Bryant, and A. Jain, “Efficient Modeling of Memory Arrays in Symbolic Simulation,” 2 CAV‘97, O. Grumberg, ed., LNCS 1254, Springer-Verlag, June 1997, pp. 388-399.
19. M.N. Velev, and R.E. Bryant, “Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation,” 2 International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS’98), B. Steffen, ed., LNCS 1384, Springer-Verlag, March-April 1998, pp. 136-150.
20. M.N. Velev, and R.E. Bryant, “Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation,”2 International Conference on Application of Concurrency to System Design (CSD‘98), IEEE Computer Society, March 1998, pp. 200-212.
21. P.J. Windley, and J.R. Burch, “Mechanically Checking a Lemma Used in an Automatic Verification Tool,” FMCAD‘96, M. Srivas and A. Camilleri, eds., LNCS 1166, Springer-Verlag, November 1996, pp. 362-376.