Verification of pipelined microprocessors by correspondence checking in symbolic ternary simulation

Proceedings - International Conference on Application of Concurrency to System Design, ACSD

Volumn 1998-March, Issue , 1998, Pages 200-212

  Velev, Miroslav N ^a   Bryant, Randal E ^b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b Carnegie Mellon University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SYSTEMS ANALYSIS;

CORRESPONDENCE CHECKING; EXECUTION SEQUENCES; FINAL STATE; INITIAL STATE; MEMORY STATE; ON THE FLIES; PIPELINED CIRCUITS; VERIFICATION METHOD;

COMPUTER AIDED SOFTWARE ENGINEERING;

EID: 85013607435     PISSN: 15504808     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSD.1998.657552     Document Type: Conference Paper

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