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Volumn 20, Issue 6, 2012, Pages 1068-1081

Pipelined parallel FFT architectures via folding transformation

Author keywords

Fast Fourier transform (FFT); Folding; Parallel processing; Pipelining; Radix 2 2; Radix 2 3; Real signals; Register minimization; Reordering circuit

Indexed keywords

FOLDING; HARDWARE COMPLEXITY; OPERATING FREQUENCY; OUTPUT SEQUENCES; PARALLEL FFT ARCHITECTURE; PARALLEL PIPELINED ARCHITECTURES; PARALLEL PROCESSING; PROPOSED ARCHITECTURES; RADIX 2; REAL SIGNALS; SERIAL ARCHITECTURE;

EID: 84861140677     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2147338     Document Type: Article
Times cited : (173)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.