메뉴 건너뛰기




Volumn , Issue , 2010, Pages 1274-1278

Parallel-pipelined radix-22 FFT architecture for real valued signals

Author keywords

FFT; Folding; Parallel Processing; Pipelining; radix 22; Real Signals

Indexed keywords

FFT; FOLDING; PARALLEL PROCESSING; RADIX 2; REAL SIGNALS;

EID: 79957983574     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.2010.5757736     Document Type: Conference Paper
Times cited : (18)

References (12)
  • 1
    • 27844612559 scopus 로고    scopus 로고
    • TDCS, OFDM, and MC-CDMA: A brief tutorial
    • Sept.
    • D. Sinha, A. H. Tewfik, "TDCS, OFDM, and MC-CDMA: a brief tutorial," IEEE Commun. Mag., vol. 43, no. 9, pp. S11-S16, Sept. 2005
    • (2005) IEEE Commun. Mag. , vol.43 , Issue.9
    • Sinha, D.1    Tewfik, A.H.2
  • 2
    • 0027659197 scopus 로고
    • Signal modeling techniques in speech recognition
    • J. W. Picone, "Signal modeling techniques in speech recognition," Proceedings of the IEEE, vol. 81, no. 9, pp. 1215-1247, 1993
    • (1993) Proceedings of the IEEE , vol.81 , Issue.9 , pp. 1215-1247
    • Picone, J.W.1
  • 4
    • 77951019433 scopus 로고    scopus 로고
    • Seizure prediction using cost-sensitive support vector machine
    • T. Netoff, Yun Park, K. K. Parhi, "Seizure prediction using cost-sensitive support vector machine," Ann. Int. Conf. EMBS 2009, pp. 3322-3325.
    • Ann. Int. Conf. EMBS 2009 , pp. 3322-3325
    • Netoff, T.1    Park, Y.2    Parhi, K.K.3
  • 5
    • 79951696294 scopus 로고    scopus 로고
    • A pipelined FFT architecture for real-valued signals
    • Dec.
    • M. Garrido, K. K. Parhi, J. Grajal, "A pipelined FFT architecture for real-valued signals," IEEE Trans. Cir. Sys. I, Reg. Papers, vol. 56, no. 12, pp. 2634-2643, Dec. 2009.
    • (2009) IEEE Trans. Cir. Sys. I, Reg. Papers , vol.56 , Issue.12 , pp. 2634-2643
    • Garrido, M.1    Parhi, K.K.2    Grajal, J.3
  • 6
    • 0029710702 scopus 로고    scopus 로고
    • A new approach to pipeline FFT processor
    • S. He and M. Torkelson, "A new approach to pipeline FFT processor," Proc. of IPPS, 1996, pp. 766-770.
    • Proc. of IPPS, 1996 , pp. 766-770
    • He, S.1    Torkelson, M.2
  • 8
    • 36248940255 scopus 로고    scopus 로고
    • High-throughput VLSI architecture for FFT computation
    • Oct.
    • C. Cheng and K. K. Parhi, "High-throughput VLSI architecture for FFT computation," IEEE Trans. Circuits and Systems.II, Exp. Briefs, vol. 54, no. 10, pp. 863-867, Oct. 2007
    • (2007) IEEE Trans. Circuits and Systems.II, Exp. Briefs , vol.54 , Issue.10 , pp. 863-867
    • Cheng, C.1    Parhi, K.K.2
  • 9
    • 54249154178 scopus 로고    scopus 로고
    • Systolic FFT Processors:A Personal Perspective
    • November
    • Earl E. Swartzlander, Jr., "Systolic FFT Processors:A Personal Perspective," Journal of Signal Processing Systems, vol. 53, November 2008, pp. 3-14.
    • (2008) Journal of Signal Processing Systems , vol.53 , pp. 3-14
    • Swartzlander Jr., E.E.1
  • 10
    • 0033115642 scopus 로고    scopus 로고
    • Radix-2 decimation in frequency algorithm for the computation of he real-valued FFT
    • Apr.
    • B. R. Sekhar, and K. M. M. Prabhu, "Radix-2 decimation in frequency algorithm for the computation of he real-valued FFT," IEEE Trans, Signal Process., vol. 47, no. 4, pp. 1181-1184, Apr. 1999
    • (1999) IEEE Trans, Signal Process. , vol.47 , Issue.4 , pp. 1181-1184
    • Sekhar, B.R.1    Prabhu, K.M.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.