A pipelined FFT architecture for real-valued signals

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 12, 2009, Pages 2634-2643

  Garrido, Mario ^a   Parhi, Keshab K ^b   Grajal, J ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

^b University of Minnesota   (United States)

Author keywords

Decimation in frequency; Decimation in time; Fast Fourier Transform (FFT); Memory reduction; Pipelined architecture; Real valued signals; Reordering circuit

Indexed keywords

FAST FOURIER TRANSFORMS;

DECIMATION IN FREQUENCIES; DECIMATION-IN-TIME; HARDWARE STRUCTURES; MEMORY REDUCTION; PIPELINED ARCHITECTURE; PIPELINED CIRCUITS; PIPELINED FFT ARCHITECTURE; PROPOSED ARCHITECTURES;

PIPELINES;

EID: 79951696294     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2017125     Document Type: Article

References (36)

1. L. Yang, K. Zhang, H. Liu, J. Huang, and S. Huang, "An efficient locally pipelined FFT processor," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 7, pp. 585-589, Jul. 2006. (Pubitemid 44111527)
2. S. He and M. Torkelson, "Design and implementation of a 1024-point pipeline FFT processor," in Proc. Custom Integr. Circuits Conf., Santa Clara, CA, May 1998, pp. 131-134.
3. M. A. Sánchez, M. Garrido, M. L. López, and J. Grajal, "Implementing the FFT algorithm on FPGA platforms: A comparative study of parallel architectures," presented at the XIX Int. Conf. Design Circuits Integr. Syst. (DCSI 2004), Bourdeaux, France, Nov. 2004.
4. W.-C. Yeh and C.-W. Jen, "High-speed and low-power split-radix FFT," IEEE Trans. Signal Process., vol. 51, no. 3, pp. 864-874, Mar. 2003.
5. Y.-N. Chang, "An efficient VLSI architecture for normal I/O order pipeline FFT design," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 12, pp. 1234-1238, Dec. 2008.
6. C. Cheng and K. K. Parhi, "High-throughput VLSI architecture for FFT computation," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 10, pp. 863-867, Oct. 2007. (Pubitemid 350123791)
7. G. Bi and E. V. Jones, "A pipelined FFT processor for world-sequential data," IEEE Tran. Acoust., Speech Signal Process., vol. 37, no. 12, pp. 1982-1985, Dec. 1989. (Pubitemid 20642710)
8. E. E. Swartzlander, W. K. W. Young, and S. J. Joseph, "A radix 4 delay commutator for fast Fourier transform processor implementation," IEEE J. Solid-State Circuits, vol. 19, no. 5, pp. 702-709, Oct. 1984.
9. Y.-W. Lin and C.-Y. Lee, "Design of an FFT/IFFT processor for MIMO OFDM systems," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 4, pp. 807-815, Apr. 2007. (Pubitemid 46621572)
10. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Englewood Cliffs, NJ: Prentice Hall, 1989.
11. H. V. Sorensen, D. L. Jones, M. T. Heideman, and C. S. Burrus, "Real-valued fast Fourier transform algorithms," IEEE Trans. Acoust., Speech Signal Process., vol. 35, no. 6, pp. 849-863, Jun. 1987.
12. M.-H. Cheng, L.-C. Chen, Y.-C. Hung, and C. M. Yang, "A real-time maximum-likelihood heart-rate estimator for wearable textile sensors," in Proc. IEEE 30th Ann. Int. Conf. EMBS, Aug. 2008, pp. 254-257.
13. R. F. Yazicioglu, P. Merken, R. Puers, and C. Van Hoof, "Low-power low-noise 8-channel EEG front-end ASIC for ambulatory acquisition systems," in Proc. European Solid-State Circuits Conf., 2006, pp. 247-250.
14. O. W. Ibraheem and N. N. Khamiss, "Design and simulation of asymmetric digital subscriber line (ADSL) modem," Proc. ICTTA, pp. 1-6, Apr. 2008.
15. H.-F. Chi and Z.-H. Lai, "A cost-effective memory-based real-valued FFT and Hermitian symmetric IFFT processor for DMT-based wireline transmission systems," in Proc. IEEE Int. Symp. Circuits Syst., May 2005, vol. 6, pp. 6006-6009.
16. Asymmetric Digital Subscriber Line (ADSL) Transceivers Extended Bandwidth ADSL2 (ADSL2plus), ITU-T Rec. G.992.5, 2005.
17. Very High Speed Digital Subscriber Line Transceivers 2 (VDSL2), ITU-T Rec. G.993.2, 2006.
18. S. C. J. Lee, F. Breyer, S. Randel, M. Schuster, J. Zeng, F. Huijskens, H. P. A. van den Boom, A. M. J. Koonen, and N. Hanik, "24-Gb/s transmission over 730 m of multimode fiber by direct modulation of an 850-nm VCSEL using discrete multi-tone modulation,," in Proc. Opt. Fiber Commun. Conf, 2007, Paper PDP 6.
19. G. Lopez-Risueno, J. Grajal, and A. Sanz-Osorio, "Digital channelized receiver based on time-frequency analysis for signal interception," IEEE Trans. Aerosp. Electron. Syst., vol. 41, no. 3, pp. 879-898, Jul. 2005. (Pubitemid 41646156)
20. Y.-H. G. Lee and C.-I. H. Chen, "Dual thresholding for digital wideband receivers with variable truncation scheme," in Proc. IEEE ISCAS, May 2009, pp. 920-923.
21. J. W. Cooley and J. W. Tukey, "An algorithm for the machine calculation of complex Fourier series," Math. Comput., vol. 19, pp. 297-301, 1965.
22. R. Storn, "A novel radix-2 pipeline architecture for the computation of the DFT," in Proc. IEEE ISCAS, Jun. 1988, vol. 2, pp. 1899-1902.
23. Y. Wu, "New FFT structures based on the Bruun algorithm," IEEE Trans. Acoust., Speech Signal Process., vol. 38, no. 1, pp. 188-191, Jan. 1990. (Pubitemid 20665402)
24. G. Bruun, "z-Transform DFT filters and FFT's," IEEE Trans. Acoust., Speech Signal Process., vol. 26, no. 1, pp. 56-63, Feb. 1978.
25. R. Storn, "Some results in fixed point error analysis of the Bruun-FTT algorithm," IEEE Trans. Signal Process., vol. 41, no. 7, pp. 2371-2375, Jul. 1993.
26. P. Duhamel, "Implementation of split-radix FFT algorithms for complex, real, and real-symmetric data," IEEE Trans. Acoust., Speech Signal Process., vol. 34, no. 2, pp. 285-295, Apr. 1986. (Pubitemid 16576060)
27. G. D. Bergland, "A fast Fourier transform algorithm for real-valued series," Commun. ACM, vol. 11, no. 10, pp. 703-710, Oct. 1968.
28. G. D. Bergland, "A radix-eight fast Fourier transform subroutine for real-valued series," IEEE Trans. Audio Electroacoust., vol. AU-17, no. 2, pp. 138-144, Jun. 1969.
29. B. R. Sekhar and K. M. M. Prabhu, "Radix-2 decimation-in-frequency algorithm for the computation of the real-valued FFT," IEEE Trans. Signal Process., vol. 47, no. 4, pp. 1181-1184, Apr. 1999.
30. D. Sundararajan, M. O. Ahmad, and M. N. S. Swamy, "Some results in fixed point error analysis of the Bruun-FTT algorithm," IEEE Trans. Signal Process., vol. 41, no. 7, pp. 2371-2375, Jul. 1997.
31. J. A. Hidalgo-López, J. C. Tejero, J. Fernández, E. Herruzo, and A. Gago, "New architecture for RFFT calculation," Electron. Lett., vol. 30, no. 22, pp. 1836-1838, Oct. 1994.
32. E. O. Brigham, The Fast Fourier Transform and Its Applications. Englewood Cliffs, NJ: Prentice-Hall, 1988.
33. W. W. Smith and J. M. Smith, Handbook of Real-Time Fast Fourier Transforms. : Wiley-IEEE Press, 1995.
34. A. Wang and A. P. Chandrakasan, "Energy-aware architectures for a real-valued FFT implementation," in Proc. Int. Symp. Low Power Electron. Des., Aug. 2003, pp. 360-365.
35. L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975.
36. M. G. Gálvez, "Desarrollo de algoritmos para detección de señales en tiempo real mediante FPGAs," M.S. thesis, ETSI de Telecomunicación, UPM, Madrid, Spain, Dec. 2004.