Exhaustive scheduling and retiming of digital signal processing systems

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 45, Issue 7, 1998, Pages 821-838

  Denk, Tracy C ^a,b   Parhi, Keshab K ^c,d  

^a IEEE   (United States)

^b LUCENT TECHNOLOGIES   (United States)

^c BROADCOM CORPORATION   (United States)

^d University of Minnesota   (United States)

Author keywords

Data flow graphs; High level synthesis; Parallel architectures; Retiming; Scheduling; Signal processing; Very large scale integration

Indexed keywords

ALGORITHMS; DIGITAL COMMUNICATION SYSTEMS; DIGITAL FILTERS; GRAPH THEORY; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

DATA FLOW GRAPHS; RETIMING;

DIGITAL SIGNAL PROCESSING;

EID: 0032117669     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.700929     Document Type: Article

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