A high-speed, low-complexity radix-2 FFT processor for MB-OFDM UWB systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 4719-4722

  Lee, Jeesung ^a   Lee, Hanno ^a   Cho, Sang In ^b   Choi, Sang Sung ^b  

^a Inha University   (South Korea)

^b Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FAST FOURIER TRANSFORMS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; THROUGHPUT; INTEGRATED CIRCUIT DESIGN; ULTRA-WIDEBAND (UWB);

ARCHITECTURE DESIGN; FFT PROCESSORS; HARDWARE COMPLEXITY; SINGLE-PATH DELAY-FEEDBACK (SDF);

BROADBAND NETWORKS;

ARCHITECTURE DESIGNS; CMOS TECHNOLOGY; HARDWARE COMPLEXITY; HIGH THROUGHPUT; MB-OFDM UWB SYSTEMS; SINGLE-PATH DELAY FEEDBACKS; SUPPLY VOLTAGES; ULTRAWIDEBAND SYSTEMS;

EID: 34547281198     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. J. Foerster, etc, "Ultra-Wideband Technology for Shor-or Medium-Range Wireless communications,"Intel Technology .Tournai Q2,2001.
2. Time Domain, "UWB Applications, Demonstration & Regulatory Update," Sept 2001 workshop, March 20, 2001.
3. A. Batra et al, "Multi-band OFDM Physical Layer Proposal, for IEEE 802.15 Task Group 3a," IEEE P802.15-03/268r3, March 2004.
4. A. Batra, J. Balakrishnan, G. R. Aiello, J. R. Foerster, A. Dabak, "Design of Multiband OFDM System for Realistic UWB Channel Environment," IEEE Trans. On Microwave Theory and Techniques, vol. 52, no. 9, pp. 2123-2138, Sept. 2004.
5. Y-W. Lin, H-Y. Liu, and G-Y. Lee, "A 1-GS/s FFT/IFFT processor for UWB applications," IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1726-1735, August, 2005.
6. S-I. Cho, S-S. Choi, S-M. Lee, and J-G. Chung, "Design of IFFT/FFT Block for MB-OFDM UWB System," Proc. CDMA international conference (CIC2004), Oct. 2004.
7. J-Y. Oh, M-S. Lim, "Fast Fourier Transform Processor Based on Low-power and Area-efficient Algorithm", Proc IEEE Asia-Pacific Conference on Adavnced System Integrated Circuits, pp. 198-201, August.2004.
8. S-M. Kim, J-G. Chung, and K. K. Parhi, "Low error fixed-width CSD multiplier With efficient sign extention," IEEE Transactions on Circuits and Systems-II, vol. 50, no. 12, Dec. 2003.