A quality of service network on chip based on a new priority arbitration mechanism

Proceedings of the International Conference on Microelectronics, ICM

Volumn , Issue , 2011, Pages

  Wissem, Chouchene ^a   Attia, Brahim ^a   Noureddine, Abid ^a   Zitouni, Abdelkrim ^a   Tourki, Rached ^a  

^a FACULTÉ DES SCIENCES DE MONASTIR   (Tunisia)

Author keywords

Arbiter; generic router; Network on Chip; Quality of Service (QoS)

Indexed keywords

ARBITER; COMPARATIVE STUDIES; DYNAMIC ARBITRATION; FPGA TECHNOLOGY; INPUT QUEUED; MESH ROUTERS; MULTIPROCESSOR SYSTEM-ON-CHIP PLATFORMS; NETWORK ON CHIP; ON CHIP COMMUNICATION; ON-CHIP NETWORKS; PARAMETERIZED DESIGN; PERFORMANCE STUDY; PRIORITY-BASED SCHEDULERS; QOS REQUIREMENTS; SATURATION POINT; SERVICE NETWORK; SOC ARCHITECTURE; SOC DESIGNS;

COMPUTER ARCHITECTURE; DISTRIBUTED COMPUTER SYSTEMS; FAULT TOLERANT COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROELECTRONICS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; QUALITY OF SERVICE;

ROUTERS;

EID: 84860659624     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2011.6177349     Document Type: Conference Paper

References (27)

1. R. Ho, K. Mai, and M. A. Horowitz, The future of wires, Proceeding IEEE, vol. 49-4, pp. 490-504, April. 89.
2. J. Liang, S. Swaminathan, and R. Tessier, "aSOC: A scalable, single chip communications architecture, "in Proc.of International Conference on Parallel Architectures and Compilation Techniques, Philadelphia, 2000, pp. 37-46.
3. W. J. Dally, "Virtual-channel flow control, "IEEE Trans. On Parallel and Distributed Systems, vol. 3-2, pp. 194-205, Mar. 1992.
4. A. Mello, L. Tedesco, N. Calazans, and F. Moraes, "Virtual Channels in Networks on Chip: Implementation and Evaluation on Hermes NoC, "in Proc. 18th Annu. Symposium on Integrated Circuits and Systems Design, New York, 2005, pp. 178-183.
5. S. Felperin, P. Raghavan, and E. Upfal, "A theory of wormhole Routing, "IEEE Trans. On Computer, vol. 45-6, pp. 704-713, June. 1996.
6. J. vidal, F. Lamotte, G. Gogniat, J.P. Diguet, and P. Soulard, "IP Reuse in an MDA MPSoPC Co-Design Approach, "in Proc .International Conference on Microelectronics, Marrakech, 2009, pp. 256-259.
7. Y.H. Tung, H.C. Lo, and S.J. Kuo, "Platform-based design automation - Platform Core Compiler, "in Proc. of VLSI, 2010, pp. 33-35.
8. L. Benini and G. De Micheli, "Network on Chips: A New SoC Paradigm, "IEEE. Computer, vol. 35-1, pp. 70-78, Jan. 2002.
9. S. Kumar, "a Network on Chip Architecture and Design Methodology, "in Proc. Of IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, 2002, pp. 105-112.
10. D. Zydek, N. Shlayan, E. Regentova, and H. Selvaraj, "Review of Packet Switching Technologies for Future NoC, "in Proc. 19th International Conference on Systems Engineering, Las Vegas, 2008, pp. 306-311.
11. L. Ni, and Am, "A survey of wormhole routing techniques in direct networks, " in IEEE .Computer, vol. 26-2, pp. 62-76, Jan. 1993.
12. E. Bolotin, and al, " QNoC: QoS architecture and design process for Network on Chip, "in Journal of Systems Architecture, vol. 50-3, pp. 105-128, Feb. 2004.
13. Daniel Andreasson and Shashi Kumar, "Improving BE traffic QoS using GT slack in NoC Systems," inNorchip, Finland, 2005, pp. 8-16.
14. E. Rijpkema, et al, "Trade Offs in The Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip, "IEEE Proceeding. Computers and Digital Techniques, vol. 150-5, pp. 294-302, Sept. 2003.
15. U. K. Ogras, et al, "Variation-Adaptive Feedback Control for Networks on-Chip with Multiple Clock Domains, "in DAC, 2008, pp. 614-619.
16. S. Badrouchi, A. Zitouni, K. Torki, and R. Tourki "Asynchronous NOC Router Design, "Journal of Computer Science, vol. 1-3, pp. 429-436, July. 2005.
17. A. Zitouni, M. Zid, K. Mejdi, S. Badrouchi, and R. Tourki, "A New generic GALS Router with Multiple QoS NOC, "International Journal of Soft Computing, vol. 2-2, pp. 249-256, 2007.
18. A. Zitouni, and R. Tourki, "Arbiter synthesis approach for SoC multi-processor systems, "in computer and Electrical engineering, vol. 43, pp. 63-77, Jan. 2008.
19. S. Felperin, P. Raghavan, and E. Upfal, " A theory of wormhole Routing, "IEEE . Computer, vol. 45-6, pp. 704-713, June. 1996.
20. A. Bartic, J. Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, and R. Lauwereins, " Highly scalable network on chip for reconfigurable systems, " in SoC, 2003, pp. 2353-2356.
21. T. Marescaux, J. -Y. Mignolet, A. Bartic, W. Moffat, D. Verkest, S. Vernalde,and R. Lauwereins, Networks on chip as hardware components of an OS for reconfigurable systems, "in Proc. Field Programmable Logic and Application, Finland, 2003, pp. 595-605.
22. F. Moraes and N. Calazan, " An infrastructure for low area overhead packet-switching network on chip, "Integration-The VLSI Journal, vol. 38-1, pp. 69-93, Oct. 2004.
23. P. P. Pande, C. Grecu, A. Ivanov, and R. Saleh, "Design of a switch for network on chip applications," in Proc. International Symposium on Circuits and Systems, 2003, pp. 217-220.
24. P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Trans. Computer, vol. 54-8, pp. 1025-1040, Aug. 2005.
25. J. Duato, S. Yalamanchili, and L. Ni, "Interconnection networks: an engineering approach, " Morgan Kaufmann Publishers, 2003.
26. D. A. Reed and D. C. Grunwald, "The performance of multicomputer interconnection networks," IEEE Trans. Computer, vol. 20-6, pp. 63-73, June. 1987.
27. B. Attia, W. Chouchene, A. Zitouni, A. Nourdin and R. Tourki, "A modular router architecture design for network on chip, " in SSD 2011, pp. 1-6.