-
2
-
-
0000328287
-
Irreversibility and Heat Generation in the Computing Process
-
July
-
R. Landauer, "Irreversibility and Heat Generation in the Computing Process," IBM Journal of Research and Development, vol. 5, no. 3, pp. 183-191, July 1961.
-
(1961)
IBM Journal of Research and Development
, vol.5
, Issue.3
, pp. 183-191
-
-
Landauer, R.1
-
3
-
-
0015680909
-
Logical Reversibility of Computation
-
Nov.
-
C. H. Bennett, "Logical Reversibility of Computation," IBM Journal of Research and Development, vol. 17, no. 6, pp. 525-532, Nov. 1973.
-
(1973)
IBM Journal of Research and Development
, vol.17
, Issue.6
, pp. 525-532
-
-
Bennett, C.H.1
-
4
-
-
0038718548
-
Synthesis of reversible logic circuits
-
June
-
V. Shende, A. Prasad, I. Markov, and J. Hayes, "Synthesis of reversible logic circuits," IEEE Trans. on CAD, vol. 22, no. 6, pp. 710 - 722, June 2003.
-
(2003)
IEEE Trans. on CAD
, vol.22
, Issue.6
, pp. 710-722
-
-
Shende, V.1
Prasad, A.2
Markov, I.3
Hayes, J.4
-
5
-
-
0043136670
-
A transformation based algorithm for reversible logic synthesis
-
ACM, June
-
D. M. Miller, D. Maslov, and G. W. Dueck, "A transformation based algorithm for reversible logic synthesis," in Design Automation Conference. ACM, June 2003, pp. 318-323.
-
(2003)
Design Automation Conference
, pp. 318-323
-
-
Miller, D.M.1
Maslov, D.2
Dueck, G.W.3
-
6
-
-
47349095028
-
ESOP-based Toffoli Gate Cascade Generation
-
IEEE, Aug.
-
K. Fazel, M. Thornton, and J. Rice, "ESOP-based Toffoli Gate Cascade Generation," in IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing. IEEE, Aug. 2007, pp. 206-209.
-
(2007)
IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing
, pp. 206-209
-
-
Fazel, K.1
Thornton, M.2
Rice, J.3
-
7
-
-
70350712413
-
BDD-based synthesis of reversible logic for large functions
-
ACM, July
-
R. Wille and R. Drechsler, "BDD-based synthesis of reversible logic for large functions," in Design Automation Conference. ACM, July 2009, pp. 270-275.
-
(2009)
Design Automation Conference
, pp. 270-275
-
-
Wille, R.1
Drechsler, R.2
-
8
-
-
79957555773
-
Determining the Minimal Number of Lines for Large Reversible Circuits
-
IEEE Computer Society, Mar.
-
R. Wille, O. Keszöcze, and R. Drechsler, "Determining the Minimal Number of Lines for Large Reversible Circuits," in Design, Automation and Test in Europe. IEEE Computer Society, Mar. 2011, pp. 1204-1207.
-
(2011)
Design, Automation and Test in Europe
, pp. 1204-1207
-
-
Wille, R.1
Keszöcze, O.2
Drechsler, R.3
-
9
-
-
77956206495
-
Reducing the number of lines in reversible circuits
-
ACM, June
-
R. Wille, M. Soeken, and R. Drechsler, "Reducing the number of lines in reversible circuits," in Design Automation Conference. ACM, June 2010, pp. 647-652.
-
(2010)
Design Automation Conference
, pp. 647-652
-
-
Wille, R.1
Soeken, M.2
Drechsler, R.3
-
10
-
-
33751058487
-
QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits
-
IEEE Computer Society, May
-
D. M. Miller and M. A. Thornton, "QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits," in Int'l Symp. on Multiple-Valued Logic. IEEE Computer Society, May 2006, pp. 30-30.
-
(2006)
Int'l Symp. on Multiple-Valued Logic
, pp. 30-30
-
-
Miller, D.M.1
Thornton, M.A.2
-
11
-
-
84978092325
-
Reversible computing
-
Automata, Languages and Programming, ser. J.W. de Bakker and J. van Leeuwen, Eds., Springer, July
-
T. Toffoli, "Reversible computing," in Automata, Languages and Programming, ser. Lecture Notes in Computer Science, J.W. de Bakker and J. van Leeuwen, Eds., vol. 85. Springer, July 1980, pp. 632-644.
-
(1980)
Lecture Notes in Computer Science
, vol.85
, pp. 632-644
-
-
Toffoli, T.1
-
12
-
-
33750189955
-
Conservative logic
-
Apr.
-
E. Fredkin and T. Toffoli, "Conservative logic," Int'l Journal of Theoretical Physics, vol. 21, no. 3, pp. 219-253, Apr. 1982.
-
(1982)
Int'l Journal of Theoretical Physics
, vol.21
, Issue.3
, pp. 219-253
-
-
Fredkin, E.1
Toffoli, T.2
-
13
-
-
25544459735
-
Reversible logic and quantum computers
-
Dec.
-
A. Peres, "Reversible logic and quantum computers," Phys. Rev. A, vol. 32, no. 6, pp. 3266-3276, Dec. 1985.
-
(1985)
Phys. Rev. A
, vol.32
, Issue.6
, pp. 3266-3276
-
-
Peres, A.1
-
14
-
-
34748841353
-
Elementary gates for quantum computation
-
Nov.
-
A. Barenco, C. H. Bennett, R. Cleve, D. P. DiVincenzo, N. Margolus, P. Shor, T. Sleator, J. A. Smolin, and H. Weinfurter, "Elementary gates for quantum computation," Phys. Rev. A, vol. 52, no. 5, pp. 3457-3467, Nov. 1995.
-
(1995)
Phys. Rev. A
, vol.52
, Issue.5
, pp. 3457-3467
-
-
Barenco, A.1
Bennett, C.H.2
Cleve, R.3
DiVincenzo, D.P.4
Margolus, N.5
Shor, P.6
Sleator, T.7
Smolin, J.A.8
Weinfurter, H.9
-
15
-
-
39749119848
-
Quantum Circuit Simplification and Level Compaction
-
Mar.
-
D. Maslov, G. W. Dueck, D. M. Miller, and C. Negrevergne, "Quantum Circuit Simplification and Level Compaction," IEEE Trans. on CAD, vol. 27, no. 3, pp. 436-444, Mar. 2008.
-
(2008)
IEEE Trans. on CAD
, vol.27
, Issue.3
, pp. 436-444
-
-
Maslov, D.1
Dueck, G.W.2
Miller, D.M.3
Negrevergne, C.4
-
16
-
-
79952457558
-
RevKit: A Toolkit for Reversible Circuit Design
-
is available at
-
M. Soeken, S. Frehse, R. Wille, and R. Drechsler, "RevKit: A Toolkit for Reversible Circuit Design," in Workshop on Reversible Computation, July 2010, pp. 69-72, RevKit is available at www.revkit.org.
-
Workshop on Reversible Computation, July 2010
, pp. 69-72
-
-
Soeken, M.1
Frehse, S.2
Wille, R.3
Drechsler, R.4
-
17
-
-
50449097451
-
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
-
IEEE Computer Society, May
-
R.Wille, D. Große, L. Teuber, G.W. Dueck, and R. Drechsler, "RevLib: An Online Resource for Reversible Functions and Reversible Circuits," in Int'l Symp. on Multiple-Valued Logic. IEEE Computer Society, May 2008, pp. 220-225.
-
(2008)
Int'l Symp. on Multiple-Valued Logic
, pp. 220-225
-
-
Wille, R.1
Große, D.2
Teuber, L.3
Dueck, G.W.4
Drechsler, R.5
-
18
-
-
84864054460
-
Reducing reversible circuit cost by adding lines
-
D. M. Miller, R. Wille, and R. Drechsler, "Reducing reversible circuit cost by adding lines," in Int'l Symp. on Multiple-Valued Logic, May 2010, pp. 217-222.
-
Int'l Symp. on Multiple-Valued Logic, May 2010
, pp. 217-222
-
-
Miller, D.M.1
Wille, R.2
Drechsler, R.3
-
19
-
-
0022769976
-
Graph-Based Algorithms for Boolean Function Manipulation
-
Aug.
-
R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. on Computers, vol. C-35, no. 8, Aug. 1986.
-
(1986)
IEEE Trans. on Computers
, vol.C-35
, Issue.8
-
-
Bryant, R.E.1
|