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Volumn , Issue , 2011, Pages 1204-1207

Determining the minimal number of lines for large reversible circuits

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT LINE; EFFICIENT COMPUTATION; EXACT APPROACH; LOW-POWER DESIGN; OPTIMAL CIRCUIT; QUANTUM COMPUTATION; RESEARCH AREAS; REVERSIBLE CIRCUITS; REVERSIBLE LOGIC; RUNTIMES; UPPER BOUND; WORST CASE;

EID: 79957555773     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (41)

References (11)
  • 2
    • 0015680909 scopus 로고
    • Logical reversibility of computation
    • C. H. Bennett, "Logical reversibility of computation," IBM J. Res. Dev, vol. 17, no. 6, pp. 525-532, 1973.
    • (1973) IBM J. Res. Dev , vol.17 , Issue.6 , pp. 525-532
    • Bennett, C.H.1
  • 5
    • 33750588847 scopus 로고    scopus 로고
    • An algorithm for synthesis of reversible logic circuits
    • P. Gupta, A. Agrawal, and N. K. Jha, "An algorithm for synthesis of reversible logic circuits," IEEE Trans. on CAD, vol. 25, no. 11, pp. 2317-2330, 2006.
    • (2006) IEEE Trans. on CAD , vol.25 , Issue.11 , pp. 2317-2330
    • Gupta, P.1    Agrawal, A.2    Jha, N.K.3
  • 6
    • 70350712413 scopus 로고    scopus 로고
    • BDD-based synthesis of reversible logic for large functions
    • R. Wille and R. Drechsler, "BDD-based synthesis of reversible logic for large functions," in Design Automation Conf., 2009, pp. 270-275.
    • Design Automation Conf., 2009 , pp. 270-275
    • Wille, R.1    Drechsler, R.2
  • 8
    • 8344281996 scopus 로고    scopus 로고
    • Reversible cascades with minimal garbage
    • D. Maslov and G. W. Dueck, "Reversible cascades with minimal garbage," IEEE Trans. on CAD, vol. 23, no. 11, pp. 1497-1509, 2004.
    • (2004) IEEE Trans. on CAD , vol.23 , Issue.11 , pp. 1497-1509
    • Maslov, D.1    Dueck, G.W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.