A novel encoding scheme for low power in network on chip links

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2012, Pages 257-261

  Sarma, Deepa N ^a   Lakshminarayanan, G ^a   Suryakiran Chavali, K V R ^a  

^a NATIONAL INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Analysis; Crosstalk; Low power; Network on chip links; Self switching; Two stage coding; Uniform power reduction

Indexed keywords

ANALYSIS; LOW POWER; NETWORK ON CHIP; POWER REDUCTIONS; SELF-SWITCHING; TWO STAGE CODING;

CROSSTALK; DATA COMMUNICATION SYSTEMS; DISTRIBUTED COMPUTER SYSTEMS; ENCODING (SYMBOLS); FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; SWITCHING;

EMBEDDED SYSTEMS;

EID: 84859918063     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2012.80     Document Type: Conference Paper

References (13)

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