Die stacking using 3D-wafer level packaging copper/polymer through-Si via technology and Cu/Sn interconnect bumping

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Civale, Y ^a   Sabuncuoglu Tezcan, D ^a   Philipsen, H G G ^a   Jaenen, P ^a   Agarwal, R ^a   Duval, F ^a   Soussan, P ^a   Travaly, Y ^a   Beyne, E ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DIE STACKING; ELECTRICAL CHARACTERIZATION; MICRO-BUMPS; POLYMER LINERS; PROCESS FLOWS; PROCESS USE; SI WAFER; SI-DRIE; THROUGH-SI VIA; WAFER LEVEL PACKAGING;

PIPE LININGS; POLYMERS; SEMICONDUCTING SILICON COMPOUNDS; SILICON; SILICON WAFERS; THREE DIMENSIONAL; WAFER BONDING;

ELECTRONICS PACKAGING;

EID: 70549089102     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306559     Document Type: Conference Paper

References (7)

1. E. Beyne, "Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits," in IEEE Technical Digest of Electron Devices Meeting, pp.23.3.1-23.3.4, 2001.
2. E. Beyne and B. Swinnen "3D system integration technologies," in IEEE International Conference on Integrated Circuit Design and Technology, pp.1-3, 2007.
3. J. Van Olmen et al., "3D stacked IC demonstration using a through silicon via First approach," in IEEE Technical Digest of International Electron Devices Meeting, pp.1-4, 2008.
4. D. S. Tezcan, N. Pham, B. Majeed, P. De Moor, W. Ruythooren, and K. Baert, "Sloped through wafer vias for 3D wafer level packaging," in Proc. 57th Electronic Components and Technology Conference, pp.643-647, 2007.
5. H. G. G. Philipsen, O. Lühn, Y. Civale, D. Sabuncuoglu Tezcan, and W. Ruythooren, "Through-silicon via technology for 3D applications," in Proc. 216th ECS Meeting, to be published, 2009.
6. E. Beyne et al., "Through-silicon via and die stacking technologies for microsystems-integration," in IEEE Technical Digest of International Electron Devices Meeting, pp.1-4, 2008.
7. R. Agarwal, W. Zhang, P. Limaye, and W. Ruythooren, "High density Cu-Sn TLP bonding for 3D integration," in Proc. 59th Electronic Components and Technology Conference, pp.345-349, 2009.