Through-silicon via technology for 3D applications

ECS Transactions

Volumn 25, Issue 38, 2009, Pages 97-107

  Philipsen, Harold G G ^a   Lühn, Ole ^a   Civale, Yann ^a   Wang, Yu Shuen ^a   Sabuncuoglu Tezcan, Deniz ^a   Ruythooren, Wouter ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; SILICON WAFERS; WAFER BONDING;

3D APPLICATION; COPPER DEPOSITION; DEFECT-FREE; ELECTRICAL CHARACTERIZATION; ELECTRODEPOSITION PROCESS; MECHANICAL POLISHING; PROCESS STEPS; THROUGH SILICON VIAS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 79952490087     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3390662     Document Type: Conference Paper

References (10)

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