A multistep tag comparison method for a low-power L2 cache

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 4, 2012, Pages 559-572

  Park, Hyunsun ^a   Yoo, Sungjoo ^a   Lee, Sunggu ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

Bloom filter (BF); cache; power consumption; tag comparison; way prediction

Indexed keywords

ASSOCIATIVE CACHE; BLOOM FILTERS; CACHE; CACHE ACCESS; CACHE ENERGY; CACHE MISS; COMPARISON METHODS; CONTROL DATA; DATA ACCESS; L2 CACHE; LIVENESS; LOW POWER; MULTI-STEP; PERFORMANCE BOUNDS; PREDICTION METHODS; TAG COMPARISON; TOTAL ENERGY CONSUMPTION; WAY PREDICTION;

BLOOMS (METAL); CACHE MEMORY; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; FORECASTING;

DATA REDUCTION;

EID: 84859042138     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2177458     Document Type: Article

References (29)

1. Qualcomm, Inc. (2004). Snapdragon Dual Core CPU Processor [Online]. Available: http://www.Qualcomm.Com/Snapdragon
2. AnandTech. (2011, Mar. 19). The Apple iPad2 Review [Online]. Available: http://www.anandtech.com/show/4225/the-ipad-2-review/4
3. ARM Ltd. (2007). PL310 Cache Controller Technical Reference Manual [Online]. Available: http://infocenter.arm.com
4. ARM Ltd. (2011). CoreLink CCI-400 Cache Coherent Interconnect (CCI) [Online]. Available: http://www.arm.com
5. K. Aisopos, C. Chou, and L. Peh, "Extending open core protocol to support system-level cache coherence," in Proc. CODES+ISSS, 2008, pp. 167-172.
6. K. Inoue, T. Ishihara, and K. Murakami, "Way-predicting set-associative cache for high performance and low energy consumption," in Proc. ISLPED, 1999, pp. 273-275. (Pubitemid 30502881)
7. M. D. Powell, A. Agarwal, T. N. Vijaykumar, M. Falsafi, and K. Roy, "Reducing set-associative cache energy via way-prediction and selective direct-mapping," in Proc. Int. Symp. Microarchitecture, 2001, pp. 54-65. (Pubitemid 34086854)
8. Z. Zhu and X. Zhang, "Access-mode predictions for low-power cache design," IEEE Micro, vol. 22, no. 2, pp. 58-71, Mar.-Apr. 2002. (Pubitemid 34434064)
9. J. Dai and L. Wang, "Way-tagged cache: An energy-efficient L2 cache architecture under write-through policy," in Proc. ISLPED, 2009, pp. 159-164.
10. C. Zhang, F. Vahid, J. Yang, and W. Najjar, "A way-halting cache for low-energy high-performance systems," in Proc. ISLPED, 2004, pp. 126-131. (Pubitemid 40454697)
11. J.-K. Peir, S.-C. Lai, S.-L. Lu, J. Stark, and K. Lai, "Bloom filtering cache misses for accurate data speculation and prefetching," in Proc. Supercomputing, 2002, pp. 189-198. (Pubitemid 35039998)
12. M. Ghosh, E. Özer, S. Ford, S. Biles, and H.-H. S. Lee, "Way guard: A segmented counting bloom filter approach to reducing energy for setassociative caches," in Proc. ISLPED, 2009, pp. 165-170.
13. G. Keramidas, P. Xekalakis, and S. Kaxiras, "Applying decay to reduce dynamic power in set-associative caches," in Proc. Int. Conf. High-Performance Embedded Architectures Compilers, 2007, pp. 38-53.
14. B. Bloom, "Space/time trade-offs in hash coding with allowable errors," Commun. ACM, vol. 13, no. 7, pp. 422-426, 1970.
15. OpenSPARCTM T2 System-on-Chip (SoC) Microarchitecture Specification, no. 820-2620-10, Sun Microsystems, Inc., May 2008 [Online]. Available: http://www.opensparc.net/pubs/t2/docs/Open SPARCT2 SoC Micro Arch Vol1.pdf
16. E. Hallnor and S. Reinhardt, "A unified compressed memory hierarchy," in Proc. Int. Symp. High-Performance Comput. Architecture, 2005, pp. 201-212. (Pubitemid 41731498)
17. L. Villa, M. Zhang, and K. Asanovic, "Dynamic zero compression for cache energy reduction," in Proc. Int. Symp. Microarchitecture, 2000, pp. 214-220. (Pubitemid 32255844)
18. M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar, "Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories," in Proc. ISLPED, 2000, pp. 90-95.
19. S. Kaxiras, Z. Hu, and M. Martonosi, "Cache decay: Exploiting generational behavior to reduce cache leakage power," in Proc. ISCA, 2001, pp. 240-251. (Pubitemid 32825409)
20. K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, "Drowsy caches: Simple techniques for reducing leakage power," in Proc. ISCA, 2002, pp. 148-157. (Pubitemid 34691858)
21. Z. Hu, S. Kaxiras, and M. Martonosi, "Timekeeping in the memory system: Predicting and optimizing memory behavior," in Proc. ISCA, 2002, pp. 209-220. (Pubitemid 34691863)
22. F. Roesner, D. Burger, and S. W. Keckler, "Counting dependence predictors," in Proc. ISCA, 2008, pp. 215-226.
23. A.-C. Lai, C. Fide, and B. Falsafi, "Dead-block prediction and deadblock correlating prefetchers," in Proc. ISCA, 2001, pp. 144-154. (Pubitemid 32825402)
24. S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, "McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures," in Proc. Int. Symp. Microarchitecture, 2009, pp. 469-480.
25. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, and G. Lowney, "Pin: Building customized program analysis tools with dynamic instrumentation," in Proc. PLDI, Jun. 2005, pp. 190-200.
26. D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob, "DRAMsim: A memory system simulator," ACM SIGARCH Comput. Architecture News, vol. 33, no. 4, pp. 100-107, Sep. 2005.
27. HP Laboratories. (2009). CACTI 6.5 [Online]. Available: http://www. hpl.hp.com/research/cacti
28. Choi et al., "Hierarchical word line scheme with decoded block selecting signals and layout method of the same," U.S. Patent 6 765 845 [Online]. Available: http://www.patsnap.com/patents/view/US6765845.html
29. A. N. Udipi, N. Muralimanohar, and N. Chatterjee, "Rethinking DRAM design and organization for energy-constrained multicores," in Proc. ISCA, 2010, pp. 175-186.