Way guard: A segmented counting bloom filter approach to reducing energy for set-associative caches

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2009, Pages 165-170

  Ghosh, Mrinmoy ^a   Özer, Emre ^b   Ford, Simon ^b   Biles, Stuart ^b   Lee, Hsien Hsin S ^c  

^a ARM Inc   (United States)

^b ARM LTD   (United Kingdom)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

B.3.2 memory structures : design styles cache memories; C.1.0 processor architecture : general; Design; Experimentation

Indexed keywords

C.1.0 [PROCESSOR ARCHITECTURE]: GENERAL; DESIGN STYLES; EXPERIMENTATION; MEMORY STRUCTURE; PROCESSOR ARCHITECTURES;

BLOOMS (METAL); COMPUTER ARCHITECTURE; DESIGN; ENERGY CONSERVATION; LOW POWER ELECTRONICS; POWER ELECTRONICS;

CACHE MEMORY;

EID: 70449723375     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594276     Document Type: Conference Paper

References (23)

1. B. Batson and T. N. Vijaykumar. Reactive-Associative Caches. Proc. of Int'l Conf. on Parallel Architectures and Compilation Techniques, 2001.
2. A. Border and M. Mitzenmacher. Network application of bloom filters: A Survey. In 40th Annual Allerton Conference on Communication, Control, and Computing, 2002.
3. B. Calder, D. Grunwald, and J. Emer. Predictive sequential associative cache. Proc. of the Int'l Symp. on High-Performance Computer Architecture, 1996.
4. Y.-J. Chang, S.-J. Ruan, and F. Lai. Sentry tag: An efficient filter scheme for low power cache. In Proc. the 7th Asia-Pacific Computer Systems Architectures Conference, 2002.
5. S. Cohen and Y. Matias. Spectral bloom filters. In Proceedings of the 2003 ACM SIGMOD International Conference on Management of Data, 2003.
6. S. Dharmapurikar, P. Krishnamurthy, T. Sproull, and J. Lockwood. Deep packet inspection using parallel bloom filters. In IEEE Hot Interconnects 12, 2003.
7. L. Fan, P. Cao, J. Almeida, and A. Broder. Summary cache: A scalable wide-area web cache sharing protocol. IEEE/ACM Transactions on Networking, 8(3):281-293, 2000.
8. M. Ghosh, E. Özer, S. Biles, and H.-H. S. Lee. Efficient System-on-Chip Energy Management with a Segmented Bloom Filter. In Proc. the 19th Int'l Conf. on Architecture of Computing Systems, 2006.
9. K. Inoue, T. Ishihara, and K. Murakami. Way-predicting set-associative cache for high performance and low energy consumption. In Proc. 1999 International Symposium on Low Power Electronics and Design, 1999.
10. K. Lawton. Welcome to the Bochs x86 PC Emulation Software Home Page. http://www.bochs.com.
11. G. Keramidas, P. Xekalakis, and S. Kaxiras. Applying Decay to Reduce Dynamic Power in Set-Associative Caches. In 2007 International Conference on High Performance Embedded Architectures and Compilers, January 2007.
12. R. Kessler, R. Jooss, A. Lebeck, and M. Hill. Inexpensive Implementations Of Set-Associativity. The 16th Annual Int'l Symp. on Computer Architecture, 1989.
13. A. Kumar, J. Xu, J. Wang, O. Spatschek, and L. Li. Space-code bloom filter for efficient per-flow traffic measurement. In Proc. IEEE INFOCOM, March 2004.
14. A. Ma, M. Zhang, and K. Asanovic.Way memoization to reduce fetch energy in instruction caches. Workshop on Complexity Effective Design, 2001.
15. N. Mehta, B. Singer, R. I. Bahar, M. Leuchtenburg, and R. Weiss. Fetch halting on critical load misses. In Proc the 22nd Int'l Conf. on Computer Design, 2004.
16. G. Memik, G. Reinman, and W. H. Mangione-Smith. Just say no: Benefits of early cache miss determination. In Proceedings of the Ninth International Symposium on High Performance Computer Architecture, 2003.
17. A. Moshovos, G. Memik, B. Falsafi, and A. Choudhary. Jetty: Snoop filtering for reduced power in smp servers. In Proceedings of International Symposium on High Performance Computer Architecture (HPCA-7), January 2001.
18. J.-K. Peir, S.-C. Lai, S.-L. Lu, J. Stark, and K. Lai. Bloom filtering cache misses for accurate data speculation and prefetching. In Proceedings of the 16th International Conference of Supercomputing, pages 189-198, 2002.
19. A. Roth. Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization. In Proc. of the 32th Int'l Symp. on Computer Architecture, 2005.
20. S. Sethumadhavan, R. Desikan, D. Burger, C. R. Moore, and S. W. Keckler. Scalable hardware memory disambiguation for high ilp processors. In Proceedings of the 36th International Symposium for Microarchitecture, 2003.
21. D. H. Woo, M. Ghosh, E. Özer, S. Biles, and H.-H. S. Lee. Reducing energy of virtual cache synonym lookup using bloom filters. In Proc. the 2006 Int'l Conf. on Compilers, Architecture and Synthesis for Embedded Systems, 2006.
22. C. Zhang, F. Vahid, J. Yang, and W. Najjar. A way-halting cache for low-energy high-performance systems. ACM Transactions on Architecture and Code Optimization (TACO), 2(1):34-54, 2005.
23. M. Zhang and K. Asanovic. Highly-associative caches for low-power processors. In Kool Chips Workshop in conj. with MICRO-33, 2000.