A way-halting cache for low-energy high-performance systems

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 126-131

  Zhang, Chuanjun ^b   Vahid, Frank ^a,c   Yang, Jun ^a   Najjar, Walid ^a  

^a Medical Center of California   (United States)

^b University of California Riverside   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Cache design; Low power techniques

Indexed keywords

BENCHMARKING; CMOS INTEGRATED CIRCUITS; DECODING; DIGITAL CIRCUITS; ENERGY DISSIPATION; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; POWER ELECTRONICS; STATIC RANDOM ACCESS STORAGE;

CACHE DESIGN; LOW POWER TECHNIQUES; POWER CONSUMPTION; WAY-HALTING CACHE;

CACHE MEMORY;

EID: 16244363688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013272     Document Type: Conference Paper

References (18)

1. Advanced Micro Devices, http://www.amd.com.
2. D. Burger and T.M. Austin, "The SimpleScalar Tool Set, Version 2.0," Univ. of Wisconsin-Madison Computer Sciences Dept. Technical Report #1342, June 1997.
3. Cadence, http://www.cadence.com
4. A. Efthymiou and J.D. Garside, "An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks," Proceedings of the International Symposium on Low Power Electronics and Design, 2002.
5. A. Hasegawa, I. Kawasaki, K. Yamada, S. Yoshioka, S. Kawasaki, and P. Biswas, "SH3: High code density, low power," IEEE Micro, Dec. 1995.
6. J. L. Hennessy and D. A. Patterson, "Computer Architecture: A Quantitative Approach," International Student Edition, third Edition. Morgan Kaufman, 2002.
7. M. Huang, J. Renau, S.M. Yoo, and J. Torrellas, "L1 Data Cache Decomposition for Energy Efficiency," International Symposium on Low Power Electronics and Design, 2001.
8. http://www.specbench.org/osg/cpu2000/
9. T. Juan, T. Lang, and J. Navarro, "The Difference-bit Cache," in Proceedings of the 27th Annual International Symposium on Computer Architecture, 1996.
10. C. Lee, M. Potkonjak and W. Mangione-Smith, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems," International Symposium on Microarchitecture, 1997.
11. L. Liu, "Cache Design with Partial Address Matching," in Proceedings of the 27th Annual International Symposium on Microarchitecture, December 1994.
12. A. Malik, B. Moyer and D. Cermak, "A Low Power Unified Cache Architecture Providing Power and Performance Flexibility," International Symposium on Low Power Electronics and Design, June 2000.
13. The MOSIS Service, http://www.mosis.org
14. M. Powell, A. Agarwal, T.N. Vijaykumar, B. Falsafi, and K. Roy, "Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping," International Symposium on Microarchitecture, 2001.
15. G. Reinmann and N.P. Jouppi. CACTI2.0: An Integrated Cache Timing and Power Model, 1999. COMPAQ Western Research Lab.
16. S. Segars, "Low power design techniques for microprocessors," International Solid-State Circuits Conference Tutorial, 2001
17. th Annual International Symposium on Computer Architecture, 1990.
18. M. Zhang and K. Asanović, "Highly-Associative Caches for Low-Power Processors," Kool Chips Workshop, in conjunction with International Symposium on Microarchitecture, Dec. 2000.