VLSI design of an SVM learning core on sequential minimal optimization algorithm

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 4, 2012, Pages 673-683

  Kuan, Ta Wen ^a   Wang, Jhing Fa ^a   Wang, Jia Ching ^b   Lin, Po Chuan ^c   Gu, Gaung Hui ^d  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^c TUNG FANG INSTITUTE OF TECHNOLOGY   (Taiwan)

^d INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Field programmable gate array (FPGA); sequential minimal optimization (SMO); support vector machine (SVM); VLSI design

Indexed keywords

INTELLECTUAL PROPERTY CORES; PROTOTYPE SYSTEM; RECOGNITION SYSTEMS; SEQUENTIAL MINIMAL OPTIMIZATION; SEQUENTIAL MINIMAL OPTIMIZATION ALGORITHMS; SUPPORT VECTOR MACHINE (SVM); VLSI DESIGN;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); OPTIMIZATION; STORMS;

SUPPORT VECTOR MACHINES;

EID: 84859009542     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2107533     Document Type: Article

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