A parallel and scalable digital architecture for training support vector machines

Journal of Zhejiang University: Science C

Volumn 11, Issue 8, 2010, Pages 620-628

  Cao, Kui Kang ^a   Shen, Hai Bin ^a   Chen, Hua Feng ^b  

^a ZHEJIANG UNIVERSITY   (China)

^b ZHEJIANG UNIVERSITY OF MEDIA AND COMMUNICATIONS   (China)

Author keywords

Field programmable gate array (FPGA); Scalable architecture; Sequential minimal optimization (SMO); Support vector machine (SVM)

Indexed keywords

COMPUTATION TIME; DIGITAL ARCHITECTURE; EMBEDDED APPLICATION; FIXED POINT ARITHMETIC; MULTIPLE PROCESSING; NUMERICAL ALGORITHMS; NUMERICAL INSTABILITY; PROPOSED ARCHITECTURES; SCALABLE ARCHITECTURES; SEQUENTIAL MINIMAL OPTIMIZATION; SEQUENTIAL MINIMAL OPTIMIZATION ALGORITHMS; SMO ALGORITHMS; SUPPORT VECTOR MACHINE (SVM); TRAINING SUPPORT VECTOR MACHINES; SUPPORT VECTOR MACHINE (SVMS);

ALGORITHMS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GEARS; LOGIC GATES; OPTIMIZATION; SCALABILITY; VECTORS; FIXED POINT ARITHMETIC; PARALLEL ARCHITECTURES;

SUPPORT VECTOR MACHINES;

EID: 77956997229     PISSN: 18691951     EISSN: 1869196X     Source Type: Journal    
DOI: 10.1631/jzus.C0910500     Document Type: Article

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