VLSI design of sequential minimal optimization algorithm for SVM learning

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 2509-2512

  Kuan, Ta Wen ^a   Wang, Jhing Fa ^a   Wang, Jia Ching ^a   Gu, Gaung Hui ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP DESIGN; INTELLECTUAL PROPERTY CORES; PROTOTYPE SYSTEM; RECOGNITION SYSTEMS; SEQUENTIAL MINIMAL OPTIMIZATION; SEQUENTIAL MINIMAL OPTIMIZATION ALGORITHMS; VLSI DESIGN;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LEARNING ALGORITHMS; OPTIMIZATION; SUPPORT VECTOR MACHINES;

SEQUENTIAL SWITCHING;

EID: 70350192366     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5118311     Document Type: Conference Paper

References (8)

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