메뉴 건너뛰기




Volumn , Issue , 2007, Pages 127-136

A generic model for formally verifying NoC communication architectures: A case study

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTERNET PROTOCOLS; LARGE SCALE SYSTEMS; MATHEMATICAL MODELS; THEOREM PROVING;

EID: 36348975796     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2007.1c     Document Type: Conference Paper
Times cited : (26)

References (33)
  • 3
    • 33745800231 scopus 로고    scopus 로고
    • A survey of research and practices of network-on-chip
    • T. Bjerregaard and S. Mahadevan. A survey of research and practices of network-on-chip. ACM Computing Surveys, 38(1), 2006.
    • (2006) ACM Computing Surveys , vol.38 , Issue.1
    • Bjerregaard, T.1    Mahadevan, S.2
  • 7
    • 84885203430 scopus 로고    scopus 로고
    • Formal verification of arbitrary network topologies
    • S. Creese and A. Roscoe. Formal verification of arbitrary network topologies. In Proc. PDPTA'99, 1999.
    • (1999) Proc. PDPTA'99
    • Creese, S.1    Roscoe, A.2
  • 9
    • 36348964510 scopus 로고    scopus 로고
    • Elements of verification
    • March
    • R. Dubey. Elements of verification. SOCcentral, March 2005.
    • (2005) SOCcentral
    • Dubey, R.1
  • 11
    • 36348958789 scopus 로고    scopus 로고
    • NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration
    • N. Genko, D. Atienza, and G. De Micheli. NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration. In Proc. ParCo'2005, 2005.
    • (2005) Proc. ParCo'2005
    • Genko, N.1    Atienza, D.2    De Micheli, G.3
  • 14
    • 0036760592 scopus 로고    scopus 로고
    • An Interconnect Architecture for Networking Systems on Chips
    • Sept
    • F. Karim, A. Nguyen, and S. Dey. An Interconnect Architecture for Networking Systems on Chips. IEEE Micro, 22(5), Sept. 2002.
    • (2002) IEEE Micro , vol.22 , Issue.5
    • Karim, F.1    Nguyen, A.2    Dey, S.3
  • 18
    • 36348979572 scopus 로고    scopus 로고
    • Formal verification: Where to use it and why
    • July
    • L. Loh. Formal verification: where to use it and why. EE-Times EDA News, July 2006.
    • (2006) EE-Times EDA News
    • Loh, L.1
  • 19
    • 3042740415 scopus 로고    scopus 로고
    • Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip
    • M. Millberg, E. Nilsson, R. Thid, and A. Jantsch. Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. In Proc. DATE'04, 2004.
    • (2004) Proc. DATE'04
    • Millberg, M.1    Nilsson, E.2    Thid, R.3    Jantsch, A.4
  • 20
    • 36349006124 scopus 로고    scopus 로고
    • Symbolic Simulation: An ACL2 Approach
    • November
    • J. Moore. Symbolic Simulation: An ACL2 Approach. In Proc. FMCAD'98, November 1998.
    • (1998) Proc. FMCAD'98
    • Moore, J.1
  • 21
    • 33747097418 scopus 로고    scopus 로고
    • A Mechanically Checked Proof of the Correctness of the Kernel of the AMD5K86 Floating-Point Division Algorithm
    • J. Moore, T. Lynch, and M. Kaufmann. A Mechanically Checked Proof of the Correctness of the Kernel of the AMD5K86 Floating-Point Division Algorithm. IEEE Trans. on Computers, 47(9), 1998.
    • (1998) IEEE Trans. on Computers , vol.47 , Issue.9
    • Moore, J.1    Lynch, T.2    Kaufmann, M.3
  • 22
    • 9544237156 scopus 로고    scopus 로고
    • HERMES: An infrastructure for low area overhead packet-switching networks on chip
    • F. Moraes, N. Calazans, A. Mello, L. Möller, and L. Ost. HERMES: an infrastructure for low area overhead packet-switching networks on chip. The VLSI Journal, 38(1), 2004.
    • (2004) The VLSI Journal , vol.38 , Issue.1
    • Moraes, F.1    Calazans, N.2    Mello, A.3    Möller, L.4    Ost, L.5
  • 24
    • 27644494723 scopus 로고    scopus 로고
    • Key Research Problems in NoC Design: A Holistic Perspective
    • September
    • U. Ogras, J. Hu, and R. Marculescu. Key Research Problems in NoC Design: A Holistic Perspective. In Proc. CODES+ISSS'2005, pages 69-74, September 2005.
    • (2005) Proc. CODES+ISSS'2005 , pp. 69-74
    • Ogras, U.1    Hu, J.2    Marculescu, R.3
  • 28
    • 36348998931 scopus 로고    scopus 로고
    • Results of the verification of a complex pipelined machine model
    • September
    • J. Sawada and W. A. Hunt. Results of the verification of a complex pipelined machine model. In Proc. CHARME'99, September 1999.
    • (1999) Proc. CHARME'99
    • Sawada, J.1    Hunt, W.A.2
  • 29
    • 33751401331 scopus 로고    scopus 로고
    • Deadlock-free routing and Component placement for irregular mesh-based networks-on-chip
    • November
    • M. Schäfer, T. Hollstein, H. Zimmer, and M. Glesner. Deadlock-free routing and Component placement for irregular mesh-based networks-on-chip. In Proc. ICCAD'05, November 2005.
    • (2005) Proc. ICCAD'05
    • Schäfer, M.1    Hollstein, T.2    Zimmer, H.3    Glesner, M.4
  • 32
    • 36348980191 scopus 로고    scopus 로고
    • Towards a Formal Theory of On Chip Communications in the ACL2 Logic
    • J. Schmaltz and D. Borrione. Towards a Formal Theory of On Chip Communications in the ACL2 Logic. In Proc. ACL2 Workshop, 2006.
    • (2006) Proc. ACL2 Workshop
    • Schmaltz, J.1    Borrione, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.