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Volumn 70, Issue , 2012, Pages 39-43

Analysis of temperature variation influence on the analog performance of 45° rotated triple-gate nMuGFETs

Author keywords

Analog operation; Early voltage; Intrinsic gain; MuGFET; Triple gate

Indexed keywords

ANALOG OPERATION; EARLY VOLTAGE; INTRINSIC GAIN; MUGFET; TRIPLE-GATE;

EID: 84858071525     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2011.11.014     Document Type: Conference Paper
Times cited : (3)

References (19)
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    • J.P. Raskin, T.M. Chung, V. Kilchytska, D. Lederer, and D. Flandre Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization IEEE Trans Electron Dev 53 5 2006 1088 1095
    • (2006) IEEE Trans Electron Dev , vol.53 , Issue.5 , pp. 1088-1095
    • Raskin, J.P.1    Chung, T.M.2    Kilchytska, V.3    Lederer, D.4    Flandre, D.5
  • 7
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    • Carrier mobility in undoped triple-gate FinFET structures and limitations of its description in terms of top and sidewall channel mobilities
    • T. Rudenko, V. Kilchytska, N. Collaert, M. Jurczak, A. Nazarov, and D. Flandre Carrier mobility in undoped triple-gate FinFET structures and limitations of its description in terms of top and sidewall channel mobilities IEEE Trans Electron Dev 55 12 2008 3532 3541
    • (2008) IEEE Trans Electron Dev , vol.55 , Issue.12 , pp. 3532-3541
    • Rudenko, T.1    Kilchytska, V.2    Collaert, N.3    Jurczak, M.4    Nazarov, A.5    Flandre, D.6
  • 11
    • 0026366830 scopus 로고
    • Measurement of threshold voltages of thin-film accumulation-mode PMOS/SOI transistors
    • A. Terao, D. Flandre, E. Lora-Tamayo, and F. Van de Wiele Measurement of threshold voltages of thin-film accumulation-mode PMOS/SOI transistors IEEE Electron Dev Lett 12 12 1991 682 684
    • (1991) IEEE Electron Dev Lett , vol.12 , Issue.12 , pp. 682-684
    • Terao, A.1    Flandre, D.2    Lora-Tamayo, E.3    Van De Wiele, F.4
  • 12
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    • Low Temperature and Silicon Thickness Influences on the Threshold Voltage of Double-Gate MOSFETs Considering a Charge Based Extraction Procedure
    • Doria RT, Pavanello MA. Low Temperature and Silicon Thickness Influences on the Threshold Voltage of Double-Gate MOSFETs Considering a Charge Based Extraction Procedure. In: Microelectronics Technology and Devices - SBMicro2009. ECS Transactions, vol. 23; 2009. p. 605-12.
    • (2009) Microelectronics Technology and Devices - SBMicro2009. ECS Transactions , vol.23 , pp. 605-12
    • Doria, R.T.1    Pavanello, M.A.2
  • 19
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    • Comparison of SOI versus bulk performances of CMOS micropower single-stage OTAs
    • D. Flandre, J.P. Eggermont, D. De Ceuster, and P. Jespers Comparison of SOI versus bulk performances of CMOS micropower single-stage OTAs Electron Lett 30 23 1994 1933 1934
    • (1994) Electron Lett , vol.30 , Issue.23 , pp. 1933-1934
    • Flandre, D.1    Eggermont, J.P.2    De Ceuster, D.3    Jespers, P.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.