Reliability analysis of enhancement-mode GaN MIS-HEMT with gate-recess structure for power supplies

IEEE International Integrated Reliability Workshop Final Report

Volumn , Issue , 2011, Pages 38-41

  Imada, T ^a   Motoyoshi, K ^a   Kanamura, M ^a   Kikkawa, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH ELECTRON MOBILITY TRANSISTORS; III-V SEMICONDUCTORS; RELIABILITY ANALYSIS; WIDE BAND GAP SEMICONDUCTORS;

DEEP LEVEL OPTICAL SPECTROSCOPY; DEEP-LEVELS; GATE RECESS; GATE-BIAS STRESS; MIS-HEMT; POSITIVE GATE BIAS; POWER SUPPLY; STRESS TEST; TRAP DENSITY;

GALLIUM NITRIDE;

EID: 84857565382     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IIRW.2011.6142584     Document Type: Conference Paper

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