3D stackable 32nm high-K/metal gate SOI embedded DRAM prototype

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 228-229

  Golz, John ^a   Safran, John ^a   He, Bishan ^a   Leu, Derek ^a   Yin, Ming ^a   Weaver, Todd ^a   Vehabovic, Adis ^a   Sun, Yan ^a   Cestero, Alberto ^a   Himmel, Ben ^a   Maier, Gary ^a   Kothandaraman, Chandrasekharan ^a   Fainstein, Daniel ^a   Barth, John ^a   Robson, Norman ^a   Kirihata, Toshiaki ^a   Rim, Ken ^a   Iyer, Subramanian ^a  

^a IBM   (United States)

Author keywords

3D; eDRAM; HKMG; TSV

Indexed keywords

3D; EDRAM; EMBEDDED DRAM; FUNCTIONAL TEST; GATE TECHNOLOGY; HKMG; THROUGH SILICON VIAS; TSV;

THREE DIMENSIONAL;

VLSI CIRCUITS;

EID: 80052672705     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. J. Barth et al., "A 45nm SOI Embedded DRAM Macros for POWER7™ 32MB On-Chip L3 Cache," JSSC, vol 46, no. 1, Jan, 2011, pp. 64-75.
2. U. Kang et. al, "8Gb 3D DDR3 SDRAM Using Through-Silicon-Via Technology," ISSCC Dig. Tech Papers, Feb. 2009, pp.130-131.
3. S. Iyer et al, "Process-design considerations for three dimensional integration, in Symp. on VLSI Tech., Dig. Tech. Papers, Jun. 2009, pp. 60-63.
4. M. Farooq et al., "3D Cu Through Silicon Via Integration and Early Reliability," 2011 Symp on VLSI Tech. (submitted).
5. M. Jacunski et. al., "A 45nm SOI compiled embedded DRAM with random cycles down to 1.3ns "2010 CICC Dig. Tech. papers.
6. 2 High Performance eDRAM Cell based on 32nm High-K/Metal SOI Technology, " 2010 IEDM Dig. Tech. Papers.
7. G. Uhlmann et. al., "A Commercial Field-Programmable Dense eFUSE Array Memory within 99.999% Sense Yield for 45nm SOI CMOS," ISSCC Dig. Tech. Papers, Feb. 2008, pp.406-407.