Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure

2010 IEEE International Interconnect Technology Conference, IITC 2010

Volumn , Issue , 2010, Pages

  Yang, Yu ^a,b   Katti, Guruprasad ^a,b   Labie, Riet ^a   Travaly, Youssef ^a   Verlinden, Bert ^b   De Wolf, Ingrid ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DIE STACKING; ELECTRICAL EVALUATIONS; INDUCED STRESS; MICRO RAMAN SPECTROSCOPY; MINIMUM DISTANCE; MOSFETS; PERFORMANCE DEGRADATION; THERMAL CYCLING TEST; THROUGH-SILICON VIA;

RAMAN SPECTROSCOPY;

CARRIER MOBILITY;

EID: 77955631216     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2010.5510710     Document Type: Conference Paper

References (4)

1. P.R. Morrow, C.-M. Park, S. Ramanathan, M.J. Kobrinsky and M. Harmes, "Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology," Electron Device Letters, IEEE , vol. 27, pp. 335-337, May 2006.
2. M. Kawashita, Y. Yoshimura and N. Tanaka, "Characterization of MOS Transistor after Through-Hole Electrode Fabrication and 3D-Assembly by Mechanical Caulking," ECTC 2009, pp. 360-364.
3. J. Van Olmen, et al., "3D stacked IC demonstration using a through Silicon Via First approach," IEDM 2008, pp.303-306.
4. K. Matsuda, K. Suzuki, K. Yamamura and Y. Kanda, "Nonlinear piezoresistance effects in silicon," J. Appl. Phys., vol.73, pp. 1838-1847, February 1993.