A 0.039um2 high performance eDRAM cell based on 32nm high-K/metal SOI technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Butt, N ^a   Mcstay, K ^a   Cestero, A ^a   Ho, H ^a   Kong, W ^a   Fang, S ^a   Krishnan, R ^a   Khan, B ^a   Tessier, A ^a   Davies, W ^a   Lee, S ^b   Zhang, Y ^b   Johnson, J ^b   Rombawa, S ^a   Takalkar, R ^a   Blauberg, A ^a   Hawkins, K V ^a   Liu, J ^a   Rosenblatt, S ^a   Goyal, P ^b   Gupta, S ^b   Ervin, J ^a   Li, Z ^a   Galis, S ^a   Barth, J ^b   Yin, M ^a   Weaver, T ^b   Li, J H ^a   Narasimha, S ^a   Parries, P ^a   Henson, W K ^a   Robson, N ^a   Kirihata, T ^a   Chudzik, M ^a   Maciejewski, E ^a   Agnello, P ^a   Stiffler, S ^a   Iyer, S S ^a   more..

^a IBM RESEARCH   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

32 NM TECHNOLOGY; CELL-BASED; CYCLE TIME; DEEP TRENCH; EMBEDDED MEMORIES; FULLY INTEGRATED; INDUSTRY BENCHMARKS; LOGIC TECHNOLOGY; METAL GATE; PRODUCT PROTOTYPE; SOI TECHNOLOGY; STATE-OF-THE-ART PERFORMANCE; TRENCH CAPACITORS;

CAPACITORS; ELECTRON DEVICES; SILICON ON INSULATOR TECHNOLOGY;

TECHNOLOGY;

EID: 79951845662     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703434     Document Type: Conference Paper

References (6)

1. J. Barth et. al., ISSCC Dig. Tech Papers, 2010.
2. http://www2.renesas.com/process/en/edramstructure.html
3. B. Greene et al., VLSI Symp. Tech. Digest, 2009.
4. Asenov et al., IEEE Trans. Elect. Dev., 2003.
5. G. Wang et al., IEDM Tech. Digest, 2009.
6. D. Wendel et. al., ISSCC Dig. Tech Papers, 2010.