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Volumn , Issue , 2003, Pages 533-536

Electrical characteristics of single, double & surround gate vertical MOSFETs with reduced overlap capacitance

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL CHARACTERISTIC; OVERLAP CAPACITANCE; SURROUND GATE; VERTICAL MOSFETS;

EID: 84856949131     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2003.1256931     Document Type: Conference Paper
Times cited : (3)

References (9)
  • 1
    • 0034453372 scopus 로고    scopus 로고
    • 50-nm vertical sidewall transistors with high channel doping concentrations
    • Schulz, T. ; Rosner, W. ; Risch, L. ; Langmann, LL; "50-nm Vertical Sidewall Transistors With High Channel Doping Concentrations", IEDM 2000, pp. 61-64
    • (2000) IEDM , pp. 61-64
    • Schulz, T.1    Rosner, W.2    Risch, L.3    Langmann, L.L.4
  • 6
    • 0033281273 scopus 로고    scopus 로고
    • High performance fully and partially depleted poly-si surrounding gate transistors
    • Cho, H. -J. ; Plummer, J. D. ; "High performance fully and partially depleted poly-Si surrounding gate transistors", 1999 Symposium on VLSI Technology Digest, pp. 31-32
    • (1999) Symposium on VLSI Technology Digest , pp. 31-32
    • Cho, H.-J.1    Plummer, J.D.2
  • 7
    • 0029717332 scopus 로고    scopus 로고
    • Vertical, fully-depleted, surrounding gate mosfets on sub-0. 1 μm thick silicon pillars
    • C. P. Auth, J. D. Plummer, "Vertical, fully-depleted, surrounding gate MOSFETs on sub-0. 1 μm thick silicon pillars", Device Research Conference, 1996, pp. 108-109
    • (1996) Device Research Conference , pp. 108-109
    • Auth, C.P.1    Plummer, J.D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.