-
1
-
-
45749124810
-
Improvement of Silicon-Based Thin Film Transistor Performances by Modifying Technological Fabrication Process Steps: A Similar Approach with ULSI Technology
-
O. Bonnaud, T. Mohammed-Brahim, Improvement of Silicon-Based Thin Film Transistor Performances by Modifying Technological Fabrication Process Steps: a Similar Approach with ULSI Technology. Electrochem. Soc Transactions, 8 (1) 51-56 (2007)
-
(2007)
Electrochem. Soc Transactions
, vol.8
, Issue.1
, pp. 51-56
-
-
Bonnaud, O.1
Mohammed-Brahim, T.2
-
2
-
-
0035340554
-
-
X. Huang, W.Chin Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y-K. Choi, K. Asano, V. Subramanian, T-J. King, J. Bokor, and C. Hu, IEEE trans. on ED, 48, no 5, 880-884 (2001).
-
(2001)
IEEE Trans. on ED
, vol.48
, Issue.5
, pp. 880-884
-
-
Huang, X.1
Chin Lee, W.2
Kuo, C.3
Hisamoto, D.4
Chang, L.5
Kedzierski, J.6
Anderson, E.7
Takeuchi, H.8
Choi, Y.-K.9
Asano, K.10
Subramanian, V.11
King, T.-J.12
Bokor, J.13
Hu, C.14
-
3
-
-
33744937051
-
-
S.K. Jayanarayanan, S. Dey, J.P. Donnelly, S.K. Banerjee, Solid-State Electronics, 50, 897 (2006).
-
(2006)
Solid-State Electronics
, vol.50
, pp. 897
-
-
Jayanarayanan, S.K.1
Dey, S.2
Donnelly, J.P.3
Banerjee, S.K.4
-
4
-
-
33947201126
-
Turning the world vertical: MOSFET with current flow perpendicular to the wafer surface
-
J. Moers, Turning the world vertical: MOSFET with current flow perpendicular to the wafer surface, Applied Physics A, 87, 531-537 (2007).
-
(2007)
Applied Physics A
, vol.87
, pp. 531-537
-
-
Moers, J.1
-
5
-
-
33847289757
-
-
K. Akarvardar, S. Cristoloveanu, M. Bawedin, P. Gentil, B.J. Blalock, D. Flandre, Solid-State Electronics, 51, 278 (2007).
-
(2007)
Solid-State Electronics
, vol.51
, pp. 278
-
-
Akarvardar, K.1
Cristoloveanu, S.2
Bawedin, M.3
Gentil, P.4
Blalock, B.J.5
Flandre, D.6
-
6
-
-
0036683901
-
Reduction of Off-Current in Self-Aligned Double-Gate TFT with Mask-Free Symmetric LDD
-
Shengdong Zhang, Ruqi Han, Johnny K. O. Sin, and Mansun Chan, Reduction of Off-Current in Self-Aligned Double-Gate TFT With Mask-Free Symmetric LDD. IEEE Trans. on ED, 49, no 8, 1490-1492 (2002)
-
(2002)
IEEE Trans. on ED
, vol.49
, Issue.8
, pp. 1490-1492
-
-
Zhang, S.1
Han, R.2
Sin, J.K.O.3
Chan, M.4
-
7
-
-
63149179321
-
-
H.D. Toure, T. Gaillard, N. Coulon, O. Bonnaud, . Electrochem. Soc Transactions, 16 (9), 165 (2008).
-
(2008)
Electrochem. Soc Transactions
, vol.16
, Issue.9
, pp. 165
-
-
Toure, H.D.1
Gaillard, T.2
Coulon, N.3
Bonnaud, O.4
-
9
-
-
33847703273
-
(22 co-authors) Inverted T channel FET (ITFET) - Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS
-
Mathew, et al. (22 co-authors) Inverted T channel FET (ITFET) - Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS. IEDM Technical Digest. IEEE International, 5 (5), 713 (2005)
-
(2005)
IEDM Technical Digest. IEEE International
, vol.5
, Issue.5
, pp. 713
-
-
Mathew1
-
10
-
-
33847248263
-
The ITFET: A Novel FinFET-Based hybrid device
-
W. Zhang, J.G. Fossum, L. Mathew, The ITFET: A Novel FinFET-Based hybrid device, IEEE Trans on ED, 53, no9, 2335-2343, (2006)
-
(2006)
IEEE Trans on ED
, vol.53
, Issue.9
, pp. 2335-2343
-
-
Zhang, W.1
Fossum, J.G.2
Mathew, L.3
-
11
-
-
84856928253
-
Can Three-Dimensional Devices Extend Moore's Law Beyond the 32 nm Technology Node?
-
Marius Orlowski and Andreas Wild, Can Three-Dimensional Devices Extend Moore's Law Beyond the 32 nm Technology Node? Electrochem. Soc Transactions, 3 (6), 1, (2006)
-
(2006)
Electrochem. Soc Transactions
, vol.3
, Issue.6
, pp. 1
-
-
Orlowski, M.1
Wild, A.2
-
12
-
-
34447300973
-
Pentacene-Based Planar- And Vertical-Type Organic Thin-Film Transistor
-
Chuan-Yi Yang, Shiau-Shin Cheng, Tzu-Min Ou, Meng-Chyi Wu, Chun-Hung Wu, Che-Hsi Chao, Shin-Yen Lin, and Yi-Jen Chan, Pentacene-Based Planar- and Vertical-Type Organic Thin-Film Transistor, IEEE Trans on ED, 54 no7, 1633-1636 (2007)
-
(2007)
IEEE Trans on ED
, vol.54
, Issue.7
, pp. 1633-1636
-
-
Yang, C.-Y.1
Cheng, S.-S.2
Ou, T.-M.3
Wu, M.-C.4
Wu, C.-H.5
Chao, C.-H.6
Lin, S.-Y.7
Chan, Y.-J.8
-
13
-
-
0029359887
-
Conduction behaviour of low temperature (≤ 600°C) Polysilicon TFT with an in-situ drain doping level
-
L. Pichon, F. Raoult, O. Bonnaud, H. Sehil, D. Briand, Conduction behaviour of low temperature (≤ 600°C) Polysilicon TFT with an in-situ drain doping level, Solid State Electronics, Vol 38, no8 (1995) pp 1515-1521
-
(1995)
Solid State Electronics
, vol.38
, Issue.8
, pp. 1515-1521
-
-
Pichon, L.1
Raoult, F.2
Bonnaud, O.3
Sehil, H.4
Briand, D.5
-
14
-
-
0032680492
-
-
O. Bonnaud, LPCVD polycrystalline silicon TFTs : state of the art and improvement of electrical characteristics, Polycrystalline Semiconductors V-Bulk Materials, Thin Films and Devices, Solid State Phenomena, Scitech Publ, 67-68, 529-540 (1999).
-
(1999)
LPCVD Polycrystalline Silicon TFTs: State of the Art and Improvement of Electrical Characteristics, Polycrystalline Semiconductors V-Bulk Materials, Thin Films and Devices, Solid State Phenomena, Scitech Publ
, vol.67-68
, pp. 529-540
-
-
Bonnaud, O.1
-
15
-
-
0028378210
-
In situ phosphorus doped VLPCVD poly-Si layers for polysilicon thin film transistors
-
M. Sarret, A. Liba, O. Bonnaud, L. Pichon, F. Raoult, In situ phosphorus doped VLPCVD poly-Si layers for polysilicon thin film transistors, IEE Part G, Polysilicon Devices and Applications, 141, no1, 19-22 (1994)
-
(1994)
IEE Part G, Polysilicon Devices and Applications
, vol.141
, Issue.1
, pp. 19-22
-
-
Sarret, M.1
Liba, A.2
Bonnaud, O.3
Pichon, L.4
Raoult, F.5
-
16
-
-
84945184802
-
Dynamic electrical characterization of CMOS-like Thin Film Transistor circuits
-
S. Crand, G. Gautier, O. Bonnaud, Dynamic electrical characterization of CMOS-like Thin Film Transistor circuits, IEEE MSE'03, Anaheim - CA (USA) 01-02 June 2003, Conf. Proc. pp 14-15 (2003)
-
(2003)
IEEE MSE'03, Anaheim - CA (USA) 01-02 June 2003, Conf. Proc.
, pp. 14-15
-
-
Crand, S.1
Gautier, G.2
Bonnaud, O.3
-
17
-
-
50249083470
-
Differential Amplifier Using Polysilicon TFTs Processed at Low Temperature to be Integrated with TFT Hall Sensor
-
6-10 Nov.
-
Jacques, E.; Le Bihan, F.; Crand, S.; Brahim, T.M., Differential Amplifier Using Polysilicon TFTs Processed at Low Temperature to be Integrated with TFT Hall Sensor, IEEE Industrial Electronics, IECON 2006 Proceedings, 3193-3198, 6-10 Nov. 2006
-
(2006)
IEEE Industrial Electronics, IECON 2006 Proceedings
, pp. 3193-3198
-
-
Jacques, E.1
Le Bihan, F.2
Crand, S.3
Brahim, T.M.4
-
18
-
-
84856853514
-
SiGe TFT
-
Abst. 795
-
D. Guillet, M. Sarret, T. Mohammed-Brahim., O. Bonnaud, SiGe TFT, Electrochem. Soc. Conference, Phoenix AZ (USA), 21-25 Oct. 2000, Conf. Abst. 795 (2000)
-
(2000)
Electrochem. Soc. Conference, Phoenix AZ (USA), 21-25 Oct. 2000, Conf.
-
-
Guillet, D.1
Sarret, M.2
Mohammed-Brahim, T.3
Bonnaud, O.4
-
19
-
-
84856843770
-
-
website
-
Corning Inc. website: www.corning.com (2009)
-
(2009)
-
-
-
20
-
-
84856939442
-
-
Technosup-Supélec, Editions-Ellipse, Paris
-
O. Bonnaud, Technologie microélectronique : Du silicium aux circuits intégrés, p. 145, Technosup-Supélec, Editions-Ellipse, Paris, (2008)
-
(2008)
Technologie Microélectronique: du Silicium Aux Circuits Intégrés
, pp. 145
-
-
Bonnaud, O.1
|