Reduction of off-current in self-aligned double-gate TFT with mask-free symmetric LDD

IEEE Transactions on Electron Devices

Volumn 49, Issue 8, 2002, Pages 1490-1492

  Zhang, Shengdong ^a   Han, Ruqi ^a   Sin, Johnny K O ^b   Chan, Mansun ^b  

^a PEKING UNIVERSITY   (China)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Double gate; Lightly doped drain (LDD); Self aligned; Thin film transistor (TFT)

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC FIELD EFFECTS; FABRICATION; GATES (TRANSISTOR); SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING;

LIGHTLY DOPED DRAIN STRUCTURES; ON OFF CURRENT RATIO;

THIN FILM TRANSISTORS;

EID: 0036683901     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.801232     Document Type: Article

References (10)

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4. Electrical characteristics of new LDD poly-Si TFT structure tolerant to process misalignment
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7. Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors
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9. Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
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