Balanced ternary addition using a gated silicon nanowire

Applied Physics Letters

Volumn 99, Issue 26, 2011, Pages

  Mol, J A ^a,b   Van Der Heijden, J ^b   Verduijn, J ^a,b   Klein, M ^c   Remacle, F ^d   Rogge, S ^a,b  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c HEBREW UNIVERSITY OF JERUSALEM   (Israel)

^d UNIVERSITY OF LIÈGE   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE IMPLEMENTATIONS; RECTIFYING BEHAVIORS; SILICON NANOWIRES; SINGLE TRANSISTORS; TERNARY ADDITION; TERNARY LOGIC; THREE-VALUED;

CAPACITANCE MEASUREMENT; ELECTRONS; HARDWARE; NANOWIRES; TRANSIENTS; TRANSISTORS;

SINGLE ELECTRON TRANSISTORS;

EID: 84855645598     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3669536     Document Type: Article

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