Dynamic programming networks for large-scale 3D chip integration

IEEE Circuits and Systems Magazine

Volumn 11, Issue 3, 2011, Pages 51-62

  Mak, Terrence ^a   Al Dujaily, Ra'Ed ^a   Zhou, Kuan ^b   Lam, Kai Pui ^c   Meng, Yicong ^d   Yakovlev, Alex ^a   Poon, Chi Sang ^d  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

^b UNIVERSITY OF NEW HAMPSHIRE   (United States)

^c CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^d MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP INTEGRATION; CMOS TECHNOLOGY; COMPUTATIONAL DELAYS; DEADLOCK DETECTION; DETECTING DEADLOCKS; DYNAMIC ROUTING; INTER-LAYER COMMUNICATION; LARGE-SCALE NETWORK; MINIMAL AREA; MULTI CORE; NETWORKS ON CHIPS; ON CHIPS; ON-CHIP SYSTEMS; OPTIMAL PATHS; PHYSICAL LAYERS; RUNTIME MANAGEMENT; TECHNOLOGICAL ADVANCES; TESTING RESULTS; THREEDIMENSIONAL (3-D); THROUGH-SILICON-VIA; TIGHTLY-COUPLED;

CLOSED LOOP CONTROL SYSTEMS; CMOS INTEGRATED CIRCUITS; COMMUNICATION; NETWORK LAYERS;

THREE DIMENSIONAL;

EID: 83755202708     PISSN: 1531636X     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCAS.2011.942102     Document Type: Review

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