-
1
-
-
0030147074
-
Closed semiring connectionist network for the Bellman-Ford computation
-
K. Lam and C. Tong, "Closed semiring connectionist network for the bellman-ford computation," IEE Proc. Comput. Digit. Tech., vol. 143, pp. 189-195, 1996. (Pubitemid 126760036)
-
(1996)
IEE Proceedings: Computers and Digital Techniques
, vol.143
, Issue.3
, pp. 189-195
-
-
Lam, K.P.1
Tong, C.W.2
-
2
-
-
85012688561
-
-
Princeton NJ: Princeton Univ. Press
-
R. Bellman, Dynamic Programming. Princeton, NJ: Princeton Univ. Press, 1957.
-
(1957)
Dynamic Programming
-
-
Bellman, R.1
-
7
-
-
36349011892
-
A hybrid analogdigital routing network for NoC dynamic routing
-
T. Mak, P. Sedcole, P. Cheung, W. Luk, and K. Lam, "A hybrid analogdigital routing network for NoC dynamic routing," in Proc. IEEE Int. Symp. Networks-on-Chip (NoC), 2007, pp. 173-182.
-
(2007)
Proc. IEEE Int. Symp. Networks-on-Chip (NoC)
, pp. 173-182
-
-
Mak, T.1
Sedcole, P.2
Cheung, P.3
Luk, W.4
Lam, K.5
-
8
-
-
72149100131
-
A DP-network for optimal dynamic routing in network-on-chip
-
T. Mak, P. Cheung, W. Luk, and K. Lam, "A DP-network for optimal dynamic routing in network-on-chip," in Proc. ACM Int. Conf. Hardware/ Software Codesign Syst. Synthesis (CODES), 2009, pp. 119-128.
-
(2009)
Proc. ACM Int. Conf. Hardware/ Software Codesign Syst. Synthesis (CODES)
, pp. 119-128
-
-
Mak, T.1
Cheung, P.2
Luk, W.3
Lam, K.4
-
9
-
-
85016294846
-
Power management in energy harvesting sensor networks
-
ACM
-
A. Kansal, J. Hsu, S. Zahedi, and M. B. Srivastava, "Power management in energy harvesting sensor networks," ACM Trans. Embedded Comput. Syst., vol. 6, no. 4, pp. 32-70, 2007.
-
(2007)
Trans. Embedded Comput. Syst.
, vol.6
, Issue.4
, pp. 32-70
-
-
Kansal, A.1
Hsu, J.2
Zahedi, S.3
Srivastava, M.B.4
-
11
-
-
0002610737
-
On a routing problem
-
R. Bellman, "On a routing problem," Q. Appl. Math., vol. 16, pp. 87-90, 1958.
-
(1958)
Q. Appl. Math.
, vol.16
, pp. 87-90
-
-
Bellman, R.1
-
15
-
-
15944424556
-
High-speed and high-precision current winner-take-all circuit
-
Mar.
-
A. Fish, V. Milrud, and O. Yadid-Pecht, "High-speed and high-precision current winner-take-all circuit," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 52, no. 3, pp. 131-135, Mar. 2005.
-
(2005)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
, vol.52
, Issue.3
, pp. 131-135
-
-
Fish, A.1
Milrud, V.2
Yadid-Pecht, O.3
-
16
-
-
0032024673
-
A CMOS analog winner-takes-all network for large-scale applications
-
Mar.
-
A. Demosthenous, S. Smedley, and J. Taylor, "A CMOS analog winner-takes-all network for large-scale applications," IEEE Trans, Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 3, pp. 300-304, Mar. 1998.
-
(1998)
IEEE Trans, Circuits Syst. I, Fundam. Theory Appl.
, vol.45
, Issue.3
, pp. 300-304
-
-
Demosthenous, A.1
Smedley, S.2
Taylor, J.3
-
17
-
-
0029247689
-
A modular current-mode highprecision winner-take-all circuit
-
Feb.
-
T. Serrano and B. Linares-Barranco, "A modular current-mode highprecision winner-take-all circuit," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 2, pp. 132-134, Feb. 1995.
-
(1995)
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
, vol.42
, Issue.2
, pp. 132-134
-
-
Serrano, T.1
Linares-Barranco, B.2
-
18
-
-
34547901410
-
A high-swing, high-speed CMOS WTA using differential flipped voltage followers
-
Aug.
-
J. Ramirez-Angulo, J. Molinar-Solis, S. Gupta, R. Carvajal, and A. Lopez-Martin, "A high-swing, high-speed CMOS WTA using differential flipped voltage followers," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 8, pp. 668-672, Aug. 2007.
-
(2007)
IEEE Trans. Circuits Syst. II, Exp. Briefs
, vol.54
, Issue.8
, pp. 668-672
-
-
Ramirez-Angulo, J.1
Molinar-Solis, J.2
Gupta, S.3
Carvajal, R.4
Lopez-Martin, A.5
-
19
-
-
75149167081
-
Low power current-mode binary-tree asynchronous min/max circuit
-
R. Dlugosz and T. Talaska, "Low power current-mode binary-tree asynchronous min/max circuit," Microelectron. J., vol. 41, no. 1, pp. 64-73, 2010.
-
(2010)
Microelectron. J.
, vol.41
, Issue.1
, pp. 64-73
-
-
Dlugosz, R.1
Talaska, T.2
-
20
-
-
0009599959
-
Low power current mode loser take-all circuit for image compression
-
B.Wilamowski, D. Jordan, and O. Kaynak, "Low power current mode loser take-all circuit for image compression," in NASA Symp. VLSI Design, 2000, pp. 7.6.1-7.6.8.
-
(2000)
NASA Symp. VLSI Design
-
-
Wilamowski, B.1
Jordan, D.2
Kaynak, O.3
-
21
-
-
0028460837
-
Analog VLSI signal processing: Why, where, and how?
-
E. Vittoz, "Analog VLSI signal processing: Why, where, and how?," J. VLSI Signal Process., vol. 8, pp. 27-44, 1994.
-
(1994)
J. VLSI Signal Process.
, vol.8
, pp. 27-44
-
-
Vittoz, E.1
-
22
-
-
34548855733
-
A current-mode analog circuit for reinforcement learning problems
-
T. Mak, K.-P. Lam, H. S. Ng, G. Rachmuth, and C.-S. Poon, "A current-mode analog circuit for reinforcement learning problems," in IEEE Int. Symp. Circuits Syst. (ISCAS), 2007, pp. 1301-1304.
-
(2007)
IEEE Int. Symp. Circuits Syst. (ISCAS)
, pp. 1301-1304
-
-
Mak, T.1
Lam, K.-P.2
Ng, H.S.3
Rachmuth, G.4
Poon, C.-S.5
-
23
-
-
0033716005
-
A current-mode CMOS loser-take-all with minimum function for neural computations
-
N. Donckers, C. Dualibe, and M. Verleysen, "A current-mode CMOS loser-take-all with minimum function for neural computations," in Proc. IEEE Symp. Circuits Syst., 2000, vol. 1, pp. 415-418.
-
(2000)
Proc. IEEE Symp. Circuits Syst.
, vol.1
, pp. 415-418
-
-
Donckers, N.1
Dualibe, C.2
Verleysen, M.3
-
24
-
-
0031996752
-
A high-precision current-mode WTA-MAX circuit with multichip capability
-
T. Serrano-Gotarredona and B. Linares-Barranco, "A high-precision current-mode WTA-MAX circuit with multichip capability," IEEE J. Solid-State Circuits, vol. 33, pp. 280-286, 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, pp. 280-286
-
-
Serrano-Gotarredona, T.1
Linares-Barranco, B.2
-
25
-
-
61649098875
-
Subthreshold FIR filter architecture for ultra low power applications
-
Proc. 18th Int. Workshop PATMOS 2008
-
B. Mishra and M. Al-Hashimi, "Subthreshold FIR filter architecture for ultra low power applications," in Proc. 18th Int. Workshop PATMOS 2008, 2008, vol. 5349, Lecture Notes in Computer Science, pp. 1-10.
-
(2008)
Lecture Notes in Computer Science
, vol.5349
, pp. 1-10
-
-
Mishra, B.1
Al-Hashimi, M.2
-
26
-
-
11944273157
-
A 180-mv subthreshold fft processor using a minimum energy design methodology
-
Jan.
-
A. Wang and A. Chandrakasan, "A 180-mv subthreshold fft processor using a minimum energy design methodology," IEEE J. Solid State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2001.
-
(2001)
IEEE J. Solid State Circuits
, vol.40
, Issue.1
, pp. 310-319
-
-
Wang, A.1
Chandrakasan, A.2
-
27
-
-
0033350671
-
Systematic width-and-length dependent CMOS transistor mismatch characterization and simulation
-
T. Serrano-Gotarredona and B. Linares-Barranco, "Systematic width-and-length dependent CMOS transistor mismatch characterization and simulation," Analog Integr. Circuits Signal Process., vol. 21, pp. 271-296, 1999.
-
(1999)
Analog Integr. Circuits Signal Process.
, vol.21
, pp. 271-296
-
-
Serrano-Gotarredona, T.1
Linares-Barranco, B.2
-
28
-
-
84899025687
-
On-chip compensation of device-mismatch effects in analog VLSI neural networks
-
M. Figueroa, S. Bridges, and C. Diorio, "On-chip compensation of device-mismatch effects in analog VLSI neural networks," in Proc. Neural Inf. Process. Syst. Conf., 2005, vol. 17, pp. 441-448.
-
(2005)
Proc. Neural Inf. Process. Syst. Conf.
, vol.17
, pp. 441-448
-
-
Figueroa, M.1
Bridges, S.2
Diorio, C.3
-
29
-
-
33646891546
-
Adaptive CMOS: From biological inspiration to systems-on-a-chip
-
DOI 10.1109/5.993402, PII S0018921902029018
-
C. Diorio, D. Hsu, and M. Figueroa, "Adaptive CMOS: From biological inspiration to systems-on-a-Chip," Proc. IEEE, vol. 90, no. 3, pp. 345-357, Mar. 2002. (Pubitemid 43779295)
-
(2002)
Proceedings of the IEEE
, vol.90
, Issue.3
, pp. 345-357
-
-
Diorio, C.1
Hsu, D.2
Figueroa, M.3
-
30
-
-
0026819378
-
Statistical modeling of device mismatch for analog mos integratedcircuits
-
C. Michael and M. Ismail, "Statistical modeling of device mismatch for analog mos integratedcircuits," IEEE J. Solid-State Circuits, vol. 27, pp. 154-166, 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 154-166
-
-
Michael, C.1
Ismail, M.2
-
31
-
-
33745134092
-
A designer's approach to device mismatch: Theory, modeling, simulation techniques, scripting, applications and examples
-
K. Papathanasiou, "A designer's approach to device mismatch: Theory, modeling, simulation techniques, scripting, applications and examples," Analog Integr. Circuits Signal Process., vol. 48, no. 2, pp. 95-106, 2006.
-
(2006)
Analog Integr. Circuits Signal Process.
, vol.48
, Issue.2
, pp. 95-106
-
-
Papathanasiou, K.1
-
33
-
-
0003987070
-
-
Upper Saddle River, NJ: Prentice- Hall
-
A. Hastings, Art of Analog Layout. Upper Saddle River, NJ: Prentice- Hall, 2005.
-
(2005)
Art of Analog Layout
-
-
Hastings, A.1
-
34
-
-
0011254490
-
Practical aspects of mixed analogue and digital design
-
ser. IEE Circuits and Systems. London, U.K.: Peter Peregrinus Ltd.
-
P. Leary, "Practical aspects of mixed analogue and digital design," in Analogue-Digital ASICs: Circuit Techniques, Design Tools and Applications, , ser. IEE Circuits and Systems. London, U.K.: Peter Peregrinus Ltd., 1991, pp. 213-238.
-
(1991)
Analogue-Digital ASICs: Circuit Techniques, Design Tools and Applications
, pp. 213-238
-
-
Leary, P.1
-
35
-
-
0034171765
-
Piecewise linear quadratic optimal control
-
Apr.
-
A. Rantzer and M. Johansson, "Piecewise linear quadratic optimal control," IEEE Trans. Autom. Control, vol. 45, no. 4, pp. 629-637, Apr. 2000.
-
(2000)
IEEE Trans. Autom. Control
, vol.45
, Issue.4
, pp. 629-637
-
-
Rantzer, A.1
Johansson, M.2
-
36
-
-
0001128590
-
Dynamic programming via convex optimization
-
A. Rantzer, "Dynamic programming via convex optimization," Proc. IFAC World Congr., pp. 491-496, 1999.
-
(1999)
Proc. IFAC World Congr.
, pp. 491-496
-
-
Rantzer, A.1
|