New Mix codes for multiple bit upsets mitigation in fault-secure memories

Microelectronics Journal

Volumn 42, Issue 3, 2011, Pages 553-561

  Zhu, Ming ^a   Xiao, Li Yi ^a   Song, Li Li ^a   Zhang, Yan Jing ^a   Luo, Hong Wei ^b  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

^b Science and Technology on Reliability Physics and Application of Electronic Component Laboratory   (China)

Author keywords

ECC; EG LDPC codes; Fault secure memory; Multibit error correction codes; Multiple bit upsets; Single event transient

Indexed keywords

ECC; EG-LDPC CODES; FAULT-SECURE MEMORY; MULTI-BIT ERROR; MULTIPLE BIT UPSETS; SINGLE EVENT TRANSIENT;

DECODING; ENCODING (SYMBOLS); ERROR CORRECTION; QUALITY ASSURANCE; REDUNDANCY;

TRANSIENTS;

EID: 79951850587     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2011.01.001     Document Type: Article

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